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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_ctrl.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/29 15:24:03 $
51 // \ \ / \ Date Created: Wed Aug 30 2006
56 //Design Name: DDR/DDR2
58 // This module is the main control logic of the memory interface. All
59 // commands are issued from here according to the burst, CAS Latency and the
63 // Rev 1.2 - Fixed auto refresh to activate bug. KP 11-19-2007
64 // Rev 1.3 - For Dual Rank parts support CS logic modified. KP. 05/08/08
65 // Rev 1.4 - AUTO_REFRESH_WAIT state modified for Auto Refresh flag asserted
66 // immediately after calibration is completed. KP. 07/28/08
67 //*****************************************************************************
73 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
74 // board design). Actual values may be different. Actual parameters values
75 // are passed from design top module ddr2_sdram module. Please refer to
76 // the ddr2_sdram module for actual values.
77 parameter BANK_WIDTH = 2,
78 parameter COL_WIDTH = 10,
79 parameter CS_BITS = 0,
81 parameter ROW_WIDTH = 14,
82 parameter ADDITIVE_LAT = 0,
83 parameter BURST_LEN = 4,
84 parameter CAS_LAT = 5,
85 parameter ECC_ENABLE = 0,
86 parameter REG_ENABLE = 1,
87 parameter TREFI_NS = 7800,
88 parameter TRAS = 40000,
89 parameter TRCD = 15000,
90 parameter TRRD = 10000,
91 parameter TRFC = 105000,
92 parameter TRP = 15000,
93 parameter TRTP = 7500,
94 parameter TWR = 15000,
95 parameter TWTR = 10000,
96 parameter CLK_PERIOD = 3000,
97 parameter MULTI_BANK_EN = 1,
98 parameter TWO_T_TIME_EN = 0,
99 parameter DDR_TYPE = 1
105 input [30:0] af_addr,
108 output ctrl_ref_flag,
110 output reg ctrl_wren,
111 output reg ctrl_rden,
112 output [ROW_WIDTH-1:0] ctrl_addr,
113 output [BANK_WIDTH-1:0] ctrl_ba,
117 output [CS_NUM-1:0] ctrl_cs_n
120 // input address split into various ranges
121 localparam ROW_RANGE_START = COL_WIDTH;
122 localparam ROW_RANGE_END = ROW_WIDTH + ROW_RANGE_START - 1;
123 localparam BANK_RANGE_START = ROW_RANGE_END + 1;
124 localparam BANK_RANGE_END = BANK_WIDTH + BANK_RANGE_START - 1;
125 localparam CS_RANGE_START = BANK_RANGE_START + BANK_WIDTH;
126 localparam CS_RANGE_END = CS_BITS + CS_RANGE_START - 1;
127 // compare address (for determining bank/row hits) split into various ranges
128 // (compare address doesn't include column bits)
129 localparam CMP_WIDTH = CS_BITS + BANK_WIDTH + ROW_WIDTH;
130 localparam CMP_ROW_RANGE_START = 0;
131 localparam CMP_ROW_RANGE_END = ROW_WIDTH + CMP_ROW_RANGE_START - 1;
132 localparam CMP_BANK_RANGE_START = CMP_ROW_RANGE_END + 1;
133 localparam CMP_BANK_RANGE_END = BANK_WIDTH + CMP_BANK_RANGE_START - 1;
134 localparam CMP_CS_RANGE_START = CMP_BANK_RANGE_END + 1;
135 localparam CMP_CS_RANGE_END = CS_BITS + CMP_CS_RANGE_START-1;
137 localparam BURST_LEN_DIV2 = BURST_LEN / 2;
138 localparam OPEN_BANK_NUM = 4;
139 localparam CS_BITS_FIX = (CS_BITS == 0) ? 1 : CS_BITS;
141 // calculation counters based on clock cycle and memory parameters
142 // TRAS: ACTIVE->PRECHARGE interval - 2
143 localparam integer TRAS_CYC = (TRAS + CLK_PERIOD)/CLK_PERIOD;
144 // TRCD: ACTIVE->READ/WRITE interval - 3 (for DDR2 factor in ADD_LAT)
145 localparam integer TRRD_CYC = (TRRD + CLK_PERIOD)/CLK_PERIOD;
146 localparam integer TRCD_CYC = (((TRCD + CLK_PERIOD)/CLK_PERIOD) >
148 ((TRCD+CLK_PERIOD)/ CLK_PERIOD) - ADDITIVE_LAT : 0;
149 // TRFC: REFRESH->REFRESH, REFRESH->ACTIVE interval - 2
150 localparam integer TRFC_CYC = (TRFC + CLK_PERIOD)/CLK_PERIOD;
151 // TRP: PRECHARGE->COMMAND interval - 2
152 // for precharge all add 1 extra clock cycle
153 localparam integer TRP_CYC = ((TRP + CLK_PERIOD)/CLK_PERIOD) +1;
154 // TRTP: READ->PRECHARGE interval - 2 (Al + BL/2 + (max (TRTP, 2tck))-2
155 localparam integer TRTP_TMP_MIN = (((TRTP + CLK_PERIOD)/CLK_PERIOD) >= 2)?
156 ((TRTP + CLK_PERIOD)/CLK_PERIOD) : 2;
157 localparam integer TRTP_CYC = TRTP_TMP_MIN + ADDITIVE_LAT
158 + BURST_LEN_DIV2 - 2;
159 // TWR: WRITE->PRECHARGE interval - 2
160 localparam integer WR_LAT = (DDR_TYPE > 0) ? CAS_LAT + ADDITIVE_LAT - 1 : 1;
161 localparam integer TWR_CYC = ((TWR + CLK_PERIOD)/CLK_PERIOD) +
162 WR_LAT + BURST_LEN_DIV2 ;
163 // TWTR: WRITE->READ interval - 3 (for DDR1, TWTR = 2 clks)
164 // DDR2 = CL-1 + BL/2 +TWTR
165 localparam integer TWTR_TMP_MIN = (TWTR + CLK_PERIOD)/CLK_PERIOD;
166 localparam integer TWTR_CYC = (DDR_TYPE > 0) ? (TWTR_TMP_MIN + (CAS_LAT -1)
167 + BURST_LEN_DIV2 ): 2;
169 // TRTW: READ->WRITE interval - 3
171 // DDR2: (BL/2) + 2. Two more clocks are added to
172 // the DDR2 counter to account for the delay in
173 // arrival of the DQS during reads (pcb trace + buffer
174 // delays + memory parameters).
175 localparam TRTW_CYC = (DDR_TYPE > 0) ? BURST_LEN_DIV2 + 4 :
176 (CAS_LAT == 25) ? 2 + BURST_LEN_DIV2 : CAS_LAT + BURST_LEN_DIV2;
178 localparam integer CAS_LAT_RD = (CAS_LAT == 25) ? 2 : CAS_LAT;
180 // Make sure all values >= 0 (some may be = 0)
181 localparam TRAS_COUNT = (TRAS_CYC > 0) ? TRAS_CYC : 0;
182 localparam TRCD_COUNT = (TRCD_CYC > 0) ? TRCD_CYC : 0;
183 localparam TRRD_COUNT = (TRRD_CYC > 0) ? TRRD_CYC : 0;
184 localparam TRFC_COUNT = (TRFC_CYC > 0) ? TRFC_CYC : 0;
185 localparam TRP_COUNT = (TRP_CYC > 0) ? TRP_CYC : 0;
186 localparam TRTP_COUNT = (TRTP_CYC > 0) ? TRTP_CYC : 0;
187 localparam TWR_COUNT = (TWR_CYC > 0) ? TWR_CYC : 0;
188 localparam TWTR_COUNT = (TWTR_CYC > 0) ? TWTR_CYC : 0;
189 localparam TRTW_COUNT = (TRTW_CYC > 0) ? TRTW_CYC : 0;
191 // Auto refresh interval
192 localparam TREFI_COUNT = ((TREFI_NS * 1000)/CLK_PERIOD) - 1;
194 // memory controller states
195 localparam CTRL_IDLE = 5'h00;
196 localparam CTRL_PRECHARGE = 5'h01;
197 localparam CTRL_PRECHARGE_WAIT = 5'h02;
198 localparam CTRL_AUTO_REFRESH = 5'h03;
199 localparam CTRL_AUTO_REFRESH_WAIT = 5'h04;
200 localparam CTRL_ACTIVE = 5'h05;
201 localparam CTRL_ACTIVE_WAIT = 5'h06;
202 localparam CTRL_BURST_READ = 5'h07;
203 localparam CTRL_READ_WAIT = 5'h08;
204 localparam CTRL_BURST_WRITE = 5'h09;
205 localparam CTRL_WRITE_WAIT = 5'h0A;
206 localparam CTRL_PRECHARGE_WAIT1 = 5'h0B;
209 reg [CMP_WIDTH-1:0] act_addr_r;
210 wire [30:0] af_addr_r;
211 reg [30:0] af_addr_r1;
212 reg [30:0] af_addr_r2;
213 reg [30:0] af_addr_r3;
220 reg [CS_BITS_FIX :0] auto_cnt_r;
222 reg [(OPEN_BANK_NUM*CMP_WIDTH)-1:0] bank_cmp_addr_r;
223 reg [OPEN_BANK_NUM-1:0] bank_hit;
224 reg [OPEN_BANK_NUM-1:0] bank_hit_r;
225 reg [OPEN_BANK_NUM-1:0] bank_hit_r1;
226 reg [OPEN_BANK_NUM-1:0] bank_valid_r;
228 reg conflict_resolved_r;
230 reg conflict_detect_r;
231 wire conflict_detect;
233 reg cs_change_sticky_r;
234 reg [ROW_WIDTH-1:0] ddr_addr_r;
235 wire [ROW_WIDTH-1:0] ddr_addr_col;
236 wire [ROW_WIDTH-1:0] ddr_addr_row;
237 reg [BANK_WIDTH-1:0] ddr_ba_r;
239 reg [CS_NUM-1:0] ddr_cs_n_r;
242 reg [4:0] next_state;
243 reg no_precharge_wait_r;
247 reg [4:0] precharge_ok_cnt_r;
252 reg [2:0] rdburst_cnt_r;
254 reg rdburst_rden_ok_r;
258 reg [4:0] rd_to_wr_cnt_r;
261 reg [11:0] refi_cnt_r;
266 /* synthesis syn_maxfan = 10 */;
270 reg [3:0] row_conflict_r;
273 reg [CMP_WIDTH-1:0] sb_open_add_r;
278 reg [2:0] trrd_cnt_r;
280 reg [2:0] two_t_enable_r;
281 reg [CS_NUM-1:0] two_t_enable_r1;
282 reg [2:0] wrburst_cnt_r;
284 reg wrburst_wren_ok_r;
287 reg [4:0] wr_to_rd_cnt_r;
290 // XST attributes for local reset "tree"
291 // synthesis attribute shreg_extract of rst_r is "no";
292 // synthesis attribute shreg_extract of rst_r1 is "no";
293 // synthesis attribute equivalent_register_removal of rst_r is "no"
295 //***************************************************************************
297 // sm_rden is used to assert read enable to the address FIFO
298 assign sm_rden = ((state_r == CTRL_BURST_WRITE) ||
299 (state_r == CTRL_BURST_READ)) ;
301 // assert read flag to the adress FIFO
302 assign ctrl_af_rden = sm_rden || rd_af_flag_r;
304 // local reset "tree" for controller logic only. Create this to ease timing
305 // on reset path. Prohibit equivalent register removal on RST_R to prevent
306 // "sharing" with other local reset trees (caution: make sure global fanout
307 // limit is set to large enough value, otherwise SLICES may be used for
308 // fanout control on RST_R.
309 always @(posedge clk) begin
314 //*****************************************************************
315 // interpret commands from Command/Address FIFO
316 //*****************************************************************
318 assign wr_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b000) ? 1'b1 : 1'b0): 1'b0;
319 assign rd_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b001) ? 1'b1 : 1'b0): 1'b0;
321 always @(posedge clk) begin
322 rd_flag_r <= rd_flag;
323 wr_flag_r <= wr_flag;
326 //////////////////////////////////////////////////
327 // The data from the address FIFO is fetched and
328 // stored in two register stages. The data will be
329 // pulled out of the second register stage whenever
330 // the state machine can handle new data from the
333 // This flag is asserted when there is no
334 // cmd & address in the pipe. When there is
335 // valid cmd & addr from the address FIFO the
336 // af_valid signals will be asserted. This flag will
337 // be set the cycle af_valid_r is de-asserted.
338 always @(posedge clk) begin
339 // for simulation purposes - to force CTRL_AF_RDEN low during reset
341 rd_af_flag_r <= 1'd0;
342 else if((ctrl_af_rden_r) ||
343 (rd_af_flag_r && (af_valid_r || af_valid_r1)))
344 rd_af_flag_r <= 1'd0;
345 else if (~af_valid_r1 || ~af_valid_r)
346 rd_af_flag_r <= 1'd1;
350 // First register stage for the cmd & add from the FIFO.
351 // The af_valid_r signal gives the status of the data
352 // in this stage. The af_valid_r will be asserted when there
353 // is valid data. This register stage will be updated
354 // 1. read to the FIFO and the FIFO not empty
355 // 2. After write and read states
356 // 3. The valid signal is not asserted in the last stage.
357 always @(posedge clk) begin
361 if (ctrl_af_rden_r || sm_rden_r || ~af_valid_r1
362 || ~af_valid_r2)begin
363 af_valid_r <= ctrl_af_rden_r;
368 // The output register in the FIFO is used. The addr
369 // and command are already registered in the FIFO.
370 assign af_addr_r = af_addr;
371 assign af_cmd_r = af_cmd;
373 // Second register stage for the cmd & add from the FIFO.
374 // The af_valid_r1 signal gives the status of the data
375 // in this stage. The af_valid_r will be asserted when there
376 // is valid data. This register stage will be updated
377 // 1. read to the FIFO and the FIFO not empty and there
378 // is no valid data on this stage
379 // 2. After write and read states
380 // 3. The valid signal is not asserted in the last stage.
381 always@(posedge clk) begin
384 af_addr_r1 <= {31{1'bx}};
385 af_cmd_r1 <= {3{1'bx}};
386 end else if (~af_valid_r1 || sm_rden_r ||
388 af_valid_r1 <= af_valid_r;
389 af_addr_r1 <= af_addr_r;
390 af_cmd_r1 <= af_cmd_r;
394 // The state machine uses the address and command in this
395 // register stage. The data is fetched from the second
396 // register stage whenever the state machine can accept new
397 // addr. The conflict flags are also generated based on the
398 // second register stage and updated when the new address
399 // is loaded for the state machine.
400 always@(posedge clk) begin
403 af_addr_r2 <= {31{1'bx}};
404 af_cmd_r2 <= {3{1'bx}};
405 bank_hit_r <= {OPEN_BANK_NUM{1'bx}};
406 bank_conflict_r <= 1'bx;
407 row_conflict_r <= 4'bx;
408 end else if(sm_rden || ~af_valid_r2)begin
409 af_valid_r2 <= af_valid_r1;
410 af_addr_r2 <= af_addr_r1;
411 af_cmd_r2 <= af_cmd_r1;
412 if(MULTI_BANK_EN)begin
413 bank_hit_r <= bank_hit;
414 row_conflict_r <= row_miss;
415 bank_conflict_r <= (~(|bank_hit));
417 bank_hit_r <= {OPEN_BANK_NUM{1'b0}};
418 bank_conflict_r <= 1'd0;
419 row_conflict_r[0] <= (af_addr_r1[CS_RANGE_END:ROW_RANGE_START]
420 != sb_open_add_r[CMP_WIDTH-1:0]);
423 end // always@ (posedge clk)
425 //detecting cs change for multi chip select case
427 if(CS_NUM > 1) begin: gen_cs_change
428 always @(posedge clk) begin
429 if(sm_rden || ~af_valid_r2)begin
430 cs_change_r <= af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=
431 af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;
432 cs_change_sticky_r <=
433 af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=
434 af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;
438 end // block: gen_cs_change
440 always @(posedge clk) begin
442 cs_change_sticky_r <= 1'd0;
447 assign conflict_detect = (MULTI_BANK_EN) ?
448 ((|(row_conflict_r[3:0] & bank_hit_r[3:0]))
449 | bank_conflict_r) & af_valid_r2 :
450 row_conflict_r[0] & af_valid_r2;
452 always @(posedge clk) begin
453 conflict_detect_r <= conflict_detect;
454 sm_rden_r <= sm_rden;
455 af_addr_r3 <= af_addr_r2;
456 ctrl_af_rden_r <= ctrl_af_rden & ~af_empty;
459 // conflict resolved signal. When this signal is asserted
460 // the conflict is resolved. The address to be compared
461 // for the conflict_resolved_r will be stored in act_add_r
462 // when the bank is opened.
463 always @(posedge clk) begin
464 conflict_resolved_r <= (act_addr_r ==
465 af_addr_r2[CS_RANGE_END:ROW_RANGE_START]);
466 if((state_r == CTRL_ACTIVE))
467 act_addr_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];
470 //***************************************************************************
471 // Bank management logic
472 // Semi-hardcoded for now for 4 banks
473 // will keep multiple banks open if MULTI_BANK_EN is true.
474 //***************************************************************************
477 generate // if multiple bank option chosen
478 if(MULTI_BANK_EN) begin: gen_multi_bank_open
480 for (bank_i = 0; bank_i < OPEN_BANK_NUM;
481 bank_i = bank_i + 1) begin: gen_bank_hit1
482 // asserted if bank address match + open bank entry is valid
485 = ((bank_cmp_addr_r[(CMP_WIDTH*(bank_i+1))-1:
486 (CMP_WIDTH*bank_i)+ROW_WIDTH] ==
487 af_addr_r1[CS_RANGE_END:BANK_RANGE_START]) &&
488 bank_valid_r[bank_i]);
489 // asserted if row address match (no check for bank entry valid, rely
490 // on this term to be used in conjunction with BANK_HIT[])
492 = (bank_cmp_addr_r[(CMP_WIDTH*bank_i)+ROW_WIDTH-1:
493 (CMP_WIDTH*bank_i)] !=
494 af_addr_r1[ROW_RANGE_END:ROW_RANGE_START]);
498 always @(posedge clk) begin
499 no_precharge_wait_r <= bank_valid_r[3] & bank_conflict_r;
500 bank_hit_r1 <= bank_hit_r;
504 no_precharge_r = ~bank_valid_r[3] & bank_conflict_r;
507 no_precharge_r1 <= no_precharge_r;
510 always @(posedge clk) begin
511 // Clear all bank valid bits during AR (i.e. since all banks get
512 // precharged during auto-refresh)
513 if ((state_r1 == CTRL_AUTO_REFRESH)) begin
514 bank_valid_r <= {(OPEN_BANK_NUM-1){1'b0}};
515 bank_cmp_addr_r <= {(OPEN_BANK_NUM*CMP_WIDTH-1){1'b0}};
517 if (state_r1 == CTRL_ACTIVE) begin
518 // 00 is always going to have the latest bank and row.
519 bank_cmp_addr_r[CMP_WIDTH-1:0]
520 <= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];
521 // This indicates the bank was activated
522 bank_valid_r[0] <= 1'b1;
524 case ({bank_hit_r1[2:0]})
526 bank_cmp_addr_r[CMP_WIDTH-1:0]
527 <= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];
528 // This indicates the bank was activated
529 bank_valid_r[0] <= 1'b1;
531 3'b010: begin //(b0->b1)
532 bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
533 <= bank_cmp_addr_r[CMP_WIDTH-1:0];
534 bank_valid_r[1] <= bank_valid_r[0];
536 3'b100:begin //(b0->b1, b1->b2)
537 bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
538 <= bank_cmp_addr_r[CMP_WIDTH-1:0];
539 bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]
540 <= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];
541 bank_valid_r[1] <= bank_valid_r[0];
542 bank_valid_r[2] <= bank_valid_r[1];
544 default: begin //(b0->b1, b1->b2, b2->b3)
545 bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
546 <= bank_cmp_addr_r[CMP_WIDTH-1:0];
547 bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]
548 <= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];
549 bank_cmp_addr_r[(4*CMP_WIDTH)-1:3*CMP_WIDTH]
550 <= bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH];
551 bank_valid_r[1] <= bank_valid_r[0];
552 bank_valid_r[2] <= bank_valid_r[1];
553 bank_valid_r[3] <= bank_valid_r[2];
559 end else begin: gen_single_bank_open // single bank option
560 always @(posedge clk) begin
561 no_precharge_r <= 1'd0;
562 no_precharge_r1 <= 1'd0;
563 no_precharge_wait_r <= 1'd0;
565 sb_open_add_r <= {CMP_WIDTH{1'b0}};
566 else if (state_r == CTRL_ACTIVE)
567 sb_open_add_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];
572 //***************************************************************************
574 //***************************************************************************
576 //*****************************************************************
577 // Write and read enable generation for PHY
578 //*****************************************************************
580 // write burst count. Counts from (BL/2 to 1).
581 // Also logic for controller write enable.
582 always @(posedge clk) begin
583 if (state_r == CTRL_BURST_WRITE) begin
584 wrburst_cnt_r <= BURST_LEN_DIV2;
585 end else if (wrburst_cnt_r >= 3'd1)
586 wrburst_cnt_r <= wrburst_cnt_r - 1;
587 end // always @ (posedge clk)
590 always @(posedge clk) begin
593 end else if (state_r == CTRL_BURST_WRITE) begin
595 end else if (wrburst_wren_ok_r)
600 always @(posedge clk) begin
601 if ((state_r == CTRL_BURST_WRITE)
602 && (BURST_LEN_DIV2 > 2))
603 wrburst_ok_r <= 1'd0;
604 else if ((wrburst_cnt_r <= 3'd3) ||
605 (BURST_LEN_DIV2 <= 2))
606 wrburst_ok_r <= 1'b1;
609 // flag to check when wrburst count has reached
610 // a value of 1. This flag is used in the ctrl_wren
612 always @(posedge clk) begin
613 if(wrburst_cnt_r == 3'd2)
614 wrburst_wren_ok_r <=1'b1;
616 wrburst_wren_ok_r <= 1'b0;
620 // read burst count. Counts from (BL/2 to 1)
621 always @(posedge clk) begin
622 if (state_r == CTRL_BURST_READ) begin
623 rdburst_cnt_r <= BURST_LEN_DIV2;
624 end else if (rdburst_cnt_r >= 3'd1)
625 rdburst_cnt_r <= rdburst_cnt_r - 1;
626 end // always @ (posedge clk)
629 always @(posedge clk) begin
632 end else if (state_r == CTRL_BURST_READ) begin
634 end else if (rdburst_rden_ok_r)
638 // the rd_burst_ok_r signal will be asserted one cycle later
639 // in multi chip select cases if the back to back read is to
640 // different chip selects. The cs_changed_sticky_r signal will
641 // be asserted only for multi chip select cases.
642 always @(posedge clk) begin
643 if ((state_r == CTRL_BURST_READ)
644 && (BURST_LEN_DIV2 > 2))
645 rdburst_ok_r <= 1'd0;
646 else if ((rdburst_cnt_r <=( 3'd3 - cs_change_sticky_r)) ||
647 (BURST_LEN_DIV2 <= 2))
648 rdburst_ok_r <= 1'b1;
651 // flag to check when rdburst count has reached
652 // a value of 1. This flag is used in the ctrl_rden
654 always @(posedge clk) begin
655 if (rdburst_cnt_r == 3'd2)
656 rdburst_rden_ok_r <= 1'b1;
658 rdburst_rden_ok_r <= 1'b0;
662 //*****************************************************************
663 // Various delay counters
664 // The counters are checked for value of <= 3 to determine the
665 // if the count values are reached during different commands.
666 // It is checked for 3 because
667 // 1. The counters are loaded during the state when the command
668 // state is reached (+1)
669 // 2. After the <= 3 condition is reached the sm takes two cycles
670 // to transition to the new command state (+2)
671 //*****************************************************************
673 // tRP count - precharge command period
674 always @(posedge clk) begin
675 if (state_r == CTRL_PRECHARGE)
676 rp_cnt_r <= TRP_COUNT;
677 else if (rp_cnt_r != 4'd0)
678 rp_cnt_r <= rp_cnt_r - 1;
681 always @(posedge clk) begin
682 if (state_r == CTRL_PRECHARGE)
684 else if (rp_cnt_r <= 4'd3)
688 // tRFC count - refresh-refresh, refresh-active
689 always @(posedge clk) begin
690 if (state_r == CTRL_AUTO_REFRESH)
691 rfc_cnt_r <= TRFC_COUNT;
692 else if (rfc_cnt_r != 8'd0)
693 rfc_cnt_r <= rfc_cnt_r - 1;
696 always @(posedge clk) begin
697 if (state_r == CTRL_AUTO_REFRESH)
699 else if(rfc_cnt_r <= 8'd3)
703 // tRCD count - active to read/write
704 always @(posedge clk) begin
705 if (state_r == CTRL_ACTIVE)
706 rcd_cnt_r <= TRCD_COUNT;
707 else if (rcd_cnt_r != 4'd0)
708 rcd_cnt_r <= rcd_cnt_r - 1;
711 always @(posedge clk) begin
712 if ((state_r == CTRL_ACTIVE)
714 rcd_cnt_ok_r <= 1'd0;
715 else if (rcd_cnt_r <= 4'd3)
719 // tRRD count - active to active
720 always @(posedge clk) begin
721 if (state_r == CTRL_ACTIVE)
722 trrd_cnt_r <= TRRD_COUNT;
723 else if (trrd_cnt_r != 3'd0)
724 trrd_cnt_r <= trrd_cnt_r - 1;
727 always @(posedge clk) begin
728 if (state_r == CTRL_ACTIVE)
729 trrd_cnt_ok_r <= 1'd0;
730 else if (trrd_cnt_r <= 3'd3)
734 // tRAS count - active to precharge
735 always @(posedge clk) begin
736 if (state_r == CTRL_ACTIVE)
737 ras_cnt_r <= TRAS_COUNT;
738 else if (ras_cnt_r != 5'd0)
739 ras_cnt_r <= ras_cnt_r - 1;
742 // counter for write to prcharge
743 // read to precharge and
744 // activate to precharge
745 // precharge_ok_cnt_r is added with trtp count,
746 // there can be cases where the sm can go from
747 // activate to read and the act->pre count time
748 // would not have been satisfied. The rd->pre
749 // time is very less. wr->pre time is almost the
751 always @(posedge clk) begin
752 if (state_r == CTRL_BURST_READ) begin
753 // assign only if the cnt is < TRTP_COUNT
754 if (precharge_ok_cnt_r < TRTP_COUNT)
755 precharge_ok_cnt_r <= TRTP_COUNT;
756 end else if (state_r == CTRL_BURST_WRITE)
757 precharge_ok_cnt_r <= TWR_COUNT;
758 else if (state_r == CTRL_ACTIVE)
759 precharge_ok_cnt_r <= TRAS_COUNT;
760 else if (precharge_ok_cnt_r != 5'd0)
761 precharge_ok_cnt_r <= precharge_ok_cnt_r - 1;
764 always @(posedge clk) begin
765 if ((state_r == CTRL_BURST_READ) ||
766 (state_r == CTRL_BURST_WRITE)||
767 (state_r == CTRL_ACTIVE))
768 precharge_ok_r <= 1'd0;
769 else if(precharge_ok_cnt_r <= 5'd3)
770 precharge_ok_r <=1'd1;
773 // write to read counter
774 // write to read includes : write latency + burst time + tWTR
775 always @(posedge clk) begin
777 wr_to_rd_cnt_r <= 5'd0;
778 else if (state_r == CTRL_BURST_WRITE)
779 wr_to_rd_cnt_r <= (TWTR_COUNT);
780 else if (wr_to_rd_cnt_r != 5'd0)
781 wr_to_rd_cnt_r <= wr_to_rd_cnt_r - 1;
784 always @(posedge clk) begin
785 if (state_r == CTRL_BURST_WRITE)
786 wr_to_rd_ok_r <= 1'd0;
787 else if (wr_to_rd_cnt_r <= 5'd3)
788 wr_to_rd_ok_r <= 1'd1;
791 // read to write counter
792 always @(posedge clk) begin
794 rd_to_wr_cnt_r <= 5'd0;
795 else if (state_r == CTRL_BURST_READ)
796 rd_to_wr_cnt_r <= (TRTW_COUNT);
797 else if (rd_to_wr_cnt_r != 5'd0)
798 rd_to_wr_cnt_r <= rd_to_wr_cnt_r - 1;
801 always @(posedge clk) begin
802 if (state_r == CTRL_BURST_READ)
803 rd_to_wr_ok_r <= 1'b0;
804 else if (rd_to_wr_cnt_r <= 5'd3)
805 rd_to_wr_ok_r <= 1'b1;
808 always @(posedge clk) begin
809 if(refi_cnt_r == (TREFI_COUNT -1))
810 refi_cnt_ok_r <= 1'b1;
812 refi_cnt_ok_r <= 1'b0;
815 // auto refresh interval counter in refresh_clk domain
816 always @(posedge clk) begin
817 if ((rst_r1) || (refi_cnt_ok_r)) begin
820 refi_cnt_r <= refi_cnt_r + 1;
822 end // always @ (posedge clk)
825 always @(posedge clk) begin
826 if (refi_cnt_ok_r) begin
831 end // always @ (posedge clk)
833 assign ctrl_ref_flag = ref_flag_r;
835 //refresh flag detect
836 //auto_ref high indicates auto_refresh requirement
837 //auto_ref is held high until auto refresh command is issued.
838 always @(posedge clk)begin
843 else if (state_r == CTRL_AUTO_REFRESH)
848 // keep track of which chip selects got auto-refreshed (avoid auto-refreshing
849 // all CS's at once to avoid current spike)
850 always @(posedge clk)begin
851 if (rst_r1 || (state_r1 == CTRL_PRECHARGE))
853 else if (state_r1 == CTRL_AUTO_REFRESH)
854 auto_cnt_r <= auto_cnt_r + 1;
857 // register for timing purposes. Extra delay doesn't really matter
858 always @(posedge clk)
859 phy_init_done_r <= phy_init_done;
861 always @(posedge clk)begin
863 state_r <= CTRL_IDLE;
864 state_r1 <= CTRL_IDLE;
866 state_r <= next_state;
871 //***************************************************************************
872 // main control state machine
873 //***************************************************************************
876 next_state = state_r;
877 (* full_case, parallel_case *) case (state_r)
879 // perform auto refresh as soon as we are done with calibration.
880 // The calibration logic does not do any refreshes.
882 next_state = CTRL_AUTO_REFRESH;
885 CTRL_PRECHARGE: begin
887 next_state = CTRL_PRECHARGE_WAIT1;
888 // when precharging an LRU bank, do not have to go to wait state
889 // since we can't possibly be activating row in same bank next
890 // disabled for 2t timing. There needs to be a gap between cmds
892 else if (no_precharge_wait_r && !TWO_T_TIME_EN)
893 next_state = CTRL_ACTIVE;
895 next_state = CTRL_PRECHARGE_WAIT;
898 CTRL_PRECHARGE_WAIT:begin
899 if (rp_cnt_ok_r)begin
901 // precharge again to make sure we close all the banks
902 next_state = CTRL_PRECHARGE;
904 next_state = CTRL_ACTIVE;
908 CTRL_PRECHARGE_WAIT1:
910 next_state = CTRL_AUTO_REFRESH;
913 next_state = CTRL_AUTO_REFRESH_WAIT;
915 CTRL_AUTO_REFRESH_WAIT:
916 //staggering Auto refresh for multi
917 // chip select designs. The SM waits
918 // for the rfc time before issuing the
919 // next auto refresh.
920 if (auto_cnt_r < (CS_NUM))begin
922 next_state = CTRL_AUTO_REFRESH;
923 end else if (rfc_ok_r)begin
925 // MIG 2.3: For deep designs if Auto Refresh
926 // flag asserted immediately after calibration is completed
927 next_state = CTRL_PRECHARGE;
928 else if ( wr_flag || rd_flag)
929 next_state = CTRL_ACTIVE;
933 next_state = CTRL_ACTIVE_WAIT;
935 CTRL_ACTIVE_WAIT: begin
936 if (rcd_cnt_ok_r) begin
937 if ((conflict_detect_r && ~conflict_resolved_r) ||
939 if (no_precharge_r1 && ~auto_ref_r && trrd_cnt_ok_r)
940 next_state = CTRL_ACTIVE;
941 else if(precharge_ok_r)
942 next_state = CTRL_PRECHARGE;
943 end else if ((wr_flag_r) && (rd_to_wr_ok_r))
944 next_state = CTRL_BURST_WRITE;
945 else if ((rd_flag_r)&& (wr_to_rd_ok_r))
946 next_state = CTRL_BURST_READ;
950 // beginning of write burst
951 CTRL_BURST_WRITE: begin
952 if (BURST_LEN_DIV2 == 1) begin
953 // special case if BL = 2 (i.e. burst lasts only one clk cycle)
955 // if we have another non-conflict write command right after the
956 // current write, then stay in this state
957 next_state = CTRL_BURST_WRITE;
959 // otherwise, if we're done with this burst, and have no write
960 // immediately scheduled after this one, wait until write-read
962 next_state = CTRL_WRITE_WAIT;
964 // otherwise BL > 2, and we have at least one more write cycle for
966 next_state = CTRL_WRITE_WAIT;
967 // continuation of write burst (also covers waiting after write burst
968 // has completed for write-read delay to pass)
971 CTRL_WRITE_WAIT: begin
972 if ((conflict_detect) || auto_ref_r) begin
973 if (no_precharge_r && ~auto_ref_r && wrburst_ok_r)
974 next_state = CTRL_ACTIVE;
975 else if (precharge_ok_r)
976 next_state = CTRL_PRECHARGE;
977 end else if (wrburst_ok_r && wr_flag)
978 next_state = CTRL_BURST_WRITE;
979 else if ((rd_flag) && (wr_to_rd_ok_r))
980 next_state = CTRL_BURST_READ;
983 CTRL_BURST_READ: begin
984 if (BURST_LEN_DIV2 == 1) begin
985 // special case if BL = 2 (i.e. burst lasts only one clk cycle)
987 next_state = CTRL_BURST_READ;
989 next_state = CTRL_READ_WAIT;
991 next_state = CTRL_READ_WAIT;
994 CTRL_READ_WAIT: begin
995 if ((conflict_detect) || auto_ref_r)begin
996 if (no_precharge_r && ~auto_ref_r && rdburst_ok_r)
997 next_state = CTRL_ACTIVE;
998 else if (precharge_ok_r)
999 next_state = CTRL_PRECHARGE;
1000 // for burst of 4 in multi chip select
1001 // if there is a change in cs wait one cycle before the
1002 // next read command. cs_change_r will be asserted.
1003 end else if (rdburst_ok_r && rd_flag && ~cs_change_r)
1004 next_state = CTRL_BURST_READ;
1005 else if (wr_flag && (rd_to_wr_ok_r))
1006 next_state = CTRL_BURST_WRITE;
1011 //***************************************************************************
1012 // control signals to memory
1013 //***************************************************************************
1015 always @(posedge clk) begin
1016 if ((state_r == CTRL_AUTO_REFRESH) ||
1017 (state_r == CTRL_ACTIVE) ||
1018 (state_r == CTRL_PRECHARGE)) begin
1019 ddr_ras_n_r <= 1'b0;
1020 two_t_enable_r[0] <= 1'b0;
1023 ddr_ras_n_r <= two_t_enable_r[0] ;
1025 ddr_ras_n_r <= 1'd1;
1026 two_t_enable_r[0] <= 1'b1;
1030 always @(posedge clk)begin
1031 if ((state_r == CTRL_BURST_WRITE) ||
1032 (state_r == CTRL_BURST_READ) ||
1033 (state_r == CTRL_AUTO_REFRESH)) begin
1034 ddr_cas_n_r <= 1'b0;
1035 two_t_enable_r[1] <= 1'b0;
1038 ddr_cas_n_r <= two_t_enable_r[1];
1040 ddr_cas_n_r <= 1'b1;
1041 two_t_enable_r[1] <= 1'b1;
1045 always @(posedge clk) begin
1046 if ((state_r == CTRL_BURST_WRITE) ||
1047 (state_r == CTRL_PRECHARGE)) begin
1049 two_t_enable_r[2] <= 1'b0;
1052 ddr_we_n_r <= two_t_enable_r[2];
1055 two_t_enable_r[2] <= 1'b1;
1059 // turn off auto-precharge when issuing commands (A10 = 0)
1060 // mapping the col add for linear addressing.
1062 if (TWO_T_TIME_EN) begin: gen_addr_col_two_t
1063 if (COL_WIDTH == ROW_WIDTH-1) begin: gen_ddr_addr_col_0
1064 assign ddr_addr_col = {af_addr_r3[COL_WIDTH-1:10], 1'b0,
1067 if (COL_WIDTH > 10) begin: gen_ddr_addr_col_1
1068 assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}},
1069 af_addr_r3[COL_WIDTH-1:10], 1'b0,
1071 end else begin: gen_ddr_addr_col_2
1072 assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}}, 1'b0,
1073 af_addr_r3[COL_WIDTH-1:0]};
1076 end else begin: gen_addr_col_one_t
1077 if (COL_WIDTH == ROW_WIDTH-1) begin: gen_ddr_addr_col_0_1
1078 assign ddr_addr_col = {af_addr_r2[COL_WIDTH-1:10], 1'b0,
1081 if (COL_WIDTH > 10) begin: gen_ddr_addr_col_1_1
1082 assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}},
1083 af_addr_r2[COL_WIDTH-1:10], 1'b0,
1085 end else begin: gen_ddr_addr_col_2_1
1086 assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}}, 1'b0,
1087 af_addr_r2[COL_WIDTH-1:0]};
1093 // Assign address during row activate
1096 assign ddr_addr_row = af_addr_r3[ROW_RANGE_END:ROW_RANGE_START];
1098 assign ddr_addr_row = af_addr_r2[ROW_RANGE_END:ROW_RANGE_START];
1102 always @(posedge clk)begin
1103 if ((state_r == CTRL_ACTIVE) ||
1104 ((state_r1 == CTRL_ACTIVE) && TWO_T_TIME_EN))
1105 ddr_addr_r <= ddr_addr_row;
1106 else if ((state_r == CTRL_BURST_WRITE) ||
1107 (state_r == CTRL_BURST_READ) ||
1108 (((state_r1 == CTRL_BURST_WRITE) ||
1109 (state_r1 == CTRL_BURST_READ)) &&
1111 ddr_addr_r <= ddr_addr_col;
1112 else if (((state_r == CTRL_PRECHARGE) ||
1113 ((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN))
1114 && auto_ref_r) begin
1115 // if we're precharging as a result of AUTO-REFRESH, precharge all banks
1116 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1117 ddr_addr_r[10] <= 1'b1;
1118 end else if ((state_r == CTRL_PRECHARGE) ||
1119 ((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN))
1120 // if we're precharging to close a specific bank/row, set A10=0
1121 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1123 ddr_addr_r <= {ROW_WIDTH{1'bx}};
1126 always @(posedge clk)begin
1127 // whenever we're precharging, we're either: (1) precharging all banks (in
1128 // which case banks bits are don't care, (2) precharging the LRU bank,
1129 // b/c we've exceeded the limit of # of banks open (need to close the LRU
1130 // bank to make room for a new one), (3) we haven't exceed the maximum #
1131 // of banks open, but we trying to open a different row in a bank that's
1133 if (((state_r == CTRL_PRECHARGE) ||
1134 ((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN)) &&
1135 bank_conflict_r && MULTI_BANK_EN)
1136 // When LRU bank needs to be closed
1137 ddr_ba_r <= bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_BANK_RANGE_END:
1138 (3*CMP_WIDTH)+CMP_BANK_RANGE_START];
1140 // Either precharge due to refresh or bank hit case
1142 ddr_ba_r <= af_addr_r3[BANK_RANGE_END:BANK_RANGE_START];
1144 ddr_ba_r <= af_addr_r2[BANK_RANGE_END:BANK_RANGE_START];
1148 // chip enable generation logic
1150 // if only one chip select, always assert it after reset
1151 if (CS_BITS == 0) begin: gen_ddr_cs_0
1152 always @(posedge clk)
1154 ddr_cs_n_r[0] <= 1'b1;
1156 ddr_cs_n_r[0] <= 1'b0;
1157 // otherwise if we have multiple chip selects
1158 end else begin: gen_ddr_cs_1
1159 if(TWO_T_TIME_EN) begin: gen_2t_cs
1160 always @(posedge clk)
1162 ddr_cs_n_r <= {CS_NUM{1'b1}};
1163 else if ((state_r1 == CTRL_AUTO_REFRESH)) begin
1164 // if auto-refreshing, only auto-refresh one CS at any time (avoid
1165 // beating on the ground plane by refreshing all CS's at same time)
1166 ddr_cs_n_r <= {CS_NUM{1'b1}};
1167 ddr_cs_n_r[auto_cnt_r] <= 1'b0;
1168 end else if (auto_ref_r && (state_r1 == CTRL_PRECHARGE)) begin
1169 ddr_cs_n_r <= {CS_NUM{1'b0}};
1170 end else if ((state_r1 == CTRL_PRECHARGE) && ( bank_conflict_r
1171 && MULTI_BANK_EN))begin
1172 // precharging the LRU bank
1173 ddr_cs_n_r <= {CS_NUM{1'b1}};
1174 ddr_cs_n_r[bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_CS_RANGE_END:
1175 (3*CMP_WIDTH)+CMP_CS_RANGE_START]] <= 1'b0;
1177 // otherwise, check the upper address bits to see which CS to assert
1178 ddr_cs_n_r <= {CS_NUM{1'b1}};
1179 ddr_cs_n_r[af_addr_r3[CS_RANGE_END:CS_RANGE_START]] <= 1'b0;
1180 end // else: !if(((state_r == CTRL_PRECHARGE) ||...
1181 end else begin: gen_1t_cs // block: gen_2t_cs
1182 always @(posedge clk)
1184 ddr_cs_n_r <= {CS_NUM{1'b1}};
1185 else if ((state_r == CTRL_AUTO_REFRESH) ) begin
1186 // if auto-refreshing, only auto-refresh one CS at any time (avoid
1187 // beating on the ground plane by refreshing all CS's at same time)
1188 ddr_cs_n_r <= {CS_NUM{1'b1}};
1189 ddr_cs_n_r[auto_cnt_r] <= 1'b0;
1190 end else if (auto_ref_r && (state_r == CTRL_PRECHARGE) ) begin
1191 ddr_cs_n_r <= {CS_NUM{1'b0}};
1192 end else if ((state_r == CTRL_PRECHARGE) &&
1193 (bank_conflict_r && MULTI_BANK_EN))begin
1194 // precharging the LRU bank
1195 ddr_cs_n_r <= {CS_NUM{1'b1}};
1196 ddr_cs_n_r[bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_CS_RANGE_END:
1197 (3*CMP_WIDTH)+CMP_CS_RANGE_START]] <= 1'b0;
1199 // otherwise, check the upper address bits to see which CS to assert
1200 ddr_cs_n_r <= {CS_NUM{1'b1}};
1201 ddr_cs_n_r[af_addr_r2[CS_RANGE_END:CS_RANGE_START]] <= 1'b0;
1202 end // else: !if(((state_r == CTRL_PRECHARGE) ||...
1203 end // block: gen_1t_cs
1207 // registring the two_t timing enable signal.
1208 // This signal will be asserted (low) when the
1209 // chip select has to be asserted.
1210 always @(posedge clk)begin
1212 two_t_enable_r1 <= {CS_NUM{1'b1}};
1214 two_t_enable_r1 <= {CS_NUM{1'b0}};
1217 assign ctrl_addr = ddr_addr_r;
1218 assign ctrl_ba = ddr_ba_r;
1219 assign ctrl_ras_n = ddr_ras_n_r;
1220 assign ctrl_cas_n = ddr_cas_n_r;
1221 assign ctrl_we_n = ddr_we_n_r;
1222 assign ctrl_cs_n = (TWO_T_TIME_EN) ?
1223 (ddr_cs_n_r | two_t_enable_r1) :