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43 //*****************************************************************************
46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_infrastructure.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/29 15:24:03 $
51 // \ \ / \ Date Created: Wed Aug 16 2006
57 // Clock generation/distribution and reset synchronization
60 // Rev 1.1 - Parameter CLK_TYPE added and logic for DIFFERENTIAL and
61 // SINGLE_ENDED added. PK. 20/6/08
62 //*****************************************************************************
66 module ddr2_infrastructure #
68 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
69 // board design). Actual values may be different. Actual parameters values
70 // are passed from design top module ddr2_sdram module. Please refer to
71 // the ddr2_sdram module for actual values.
72 parameter CLK_PERIOD = 3000,
73 parameter CLK_TYPE = "DIFFERENTIAL",
74 parameter DLL_FREQ_MODE = "HIGH",
75 parameter RST_ACT_LOW = 1
89 input idelay_ctrl_rdy,
96 // # of clock cycles to delay deassertion of reset. Needs to be a fairly
97 // high number not so much for metastability protection, but to give time
98 // for reset (i.e. stable clock cycles) to propagate through all state
99 // machines and to all control signals (i.e. not all control signals have
100 // resets, instead they rely on base state logic being reset, and the effect
101 // of that reset propagating through the logic). Need this because we may not
102 // be getting stable clock cycles while reset asserted (i.e. since reset
103 // depends on DCM lock status)
104 localparam RST_SYNC_NUM = 25;
105 localparam CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
116 reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
117 reg [RST_SYNC_NUM-1:0] rst200_sync_r /* synthesis syn_maxfan = 10 */;
118 reg [RST_SYNC_NUM-1:0] rst90_sync_r /* synthesis syn_maxfan = 10 */;
119 reg [(RST_SYNC_NUM/2)-1:0] rstdiv0_sync_r /* synthesis syn_maxfan = 10 */;
124 assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;
126 assign clk0 = clk0_bufg;
127 assign clk90 = clk90_bufg;
128 assign clk200 = clk200_bufg;
129 assign clkdiv0 = clkdiv0_bufg;
132 if(CLK_TYPE == "DIFFERENTIAL") begin : DIFF_ENDED_CLKS_INST
133 //***************************************************************************
134 // Differential input clock input buffers
135 //***************************************************************************
137 IBUFGDS_LVPECL_25 SYS_CLK_INST
144 IBUFGDS_LVPECL_25 IDLY_CLK_INST
151 end else if(CLK_TYPE == "SINGLE_ENDED") begin : SINGLE_ENDED_CLKS_INST
152 //**************************************************************************
153 // Single ended input clock input buffers
154 //**************************************************************************
156 // AM -- edits: changed IBUFG to BUF
179 //***************************************************************************
180 // Global clock generation and distribution
181 //***************************************************************************
185 .CLKIN_PERIOD (CLK_PERIOD_NS),
187 .DLL_FREQUENCY_MODE (DLL_FREQ_MODE),
188 .DUTY_CYCLE_CORRECTION ("TRUE"),
189 .FACTORY_JF (16'hF0F0)
199 .CLKDV (dcm_clkdiv0),
204 .CLKIN (sys_clk_ibufg),
227 //***************************************************************************
228 // Reset synchronization
230 // 1. shut down the whole operation if the DCM hasn't yet locked (and by
231 // inference, this means that external SYS_RST_IN has been asserted -
232 // DCM deasserts DCM_LOCK as soon as SYS_RST_IN asserted)
233 // 2. In the case of all resets except rst200, also assert reset if the
234 // IDELAY master controller is not yet ready
235 // 3. asynchronously assert reset. This was we can assert reset even if
236 // there is no clock (needed for things like 3-stating output buffers).
237 // reset deassertion is synchronous.
238 //***************************************************************************
240 assign rst_tmp = sys_rst | ~dcm_lock | ~idelay_ctrl_rdy;
242 // synthesis attribute max_fanout of rst0_sync_r is 10
243 always @(posedge clk0_bufg or posedge rst_tmp)
245 rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
247 // logical left shift by one (pads with 0)
248 rst0_sync_r <= rst0_sync_r << 1;
250 // synthesis attribute max_fanout of rstdiv0_sync_r is 10
251 always @(posedge clkdiv0_bufg or posedge rst_tmp)
253 rstdiv0_sync_r <= {(RST_SYNC_NUM/2){1'b1}};
255 // logical left shift by one (pads with 0)
256 rstdiv0_sync_r <= rstdiv0_sync_r << 1;
258 // synthesis attribute max_fanout of rst90_sync_r is 10
259 always @(posedge clk90_bufg or posedge rst_tmp)
261 rst90_sync_r <= {RST_SYNC_NUM{1'b1}};
263 rst90_sync_r <= rst90_sync_r << 1;
265 // make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg
266 // synthesis attribute max_fanout of rst200_sync_r is 10
267 always @(posedge clk200_bufg or negedge dcm_lock)
269 rst200_sync_r <= {RST_SYNC_NUM{1'b1}};
271 rst200_sync_r <= rst200_sync_r << 1;
274 assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
275 assign rst90 = rst90_sync_r[RST_SYNC_NUM-1];
276 assign rst200 = rst200_sync_r[RST_SYNC_NUM-1];
277 assign rstdiv0 = rstdiv0_sync_r[(RST_SYNC_NUM/2)-1];