src/edu/berkeley/fleet/fpga/ddr2/ddr2_mem_if_top.v

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  44 //   ____  ____
  45 //  /   /\/   /
  46 // /___/  \  /    Vendor: Xilinx
  47 // \   \   \/     Version: 2.3
  48 //  \   \         Application: MIG
  49 //  /   /         Filename: ddr2_mem_if_top.v
  50 // /___/   /\     Date Last Modified: $Date: 2008/07/22 15:41:06 $
  51 // \   \  /  \    Date Created: Wed Aug 16 2006
  52 //  \___\/\___\
  53 //
  54 //Device: Virtex-5
  55 //Design Name: DDR/DDR2
  56 //Purpose:
  57 //   Top-level for parameterizable (DDR or DDR2) memory interface
  58 //Reference:
  59 //Revision History:
  60 //*****************************************************************************
  61
  62 `timescale 1ns/1ps
  63
  64 module ddr2_mem_if_top #
  65   (
  66    // Following parameters are for 72-bit RDIMM design (for ML561 Reference
  67    // board design). Actual values may be different. Actual parameters values
  68    // are passed from design top module ddr2_sdram module. Please refer to
  69    // the ddr2_sdram module for actual values.
  70    parameter BANK_WIDTH            = 2,
  71    parameter CKE_WIDTH             = 1,
  72    parameter CLK_WIDTH             = 1,
  73    parameter COL_WIDTH             = 10,
  74    parameter CS_BITS               = 0,
  75    parameter CS_NUM                = 1,
  76    parameter CS_WIDTH              = 1,
  77    parameter USE_DM_PORT           = 1,
  78    parameter DM_WIDTH              = 9,
  79    parameter DQ_WIDTH              = 72,
  80    parameter DQ_BITS               = 7,
  81    parameter DQ_PER_DQS            = 8,
  82    parameter DQS_BITS              = 4,
  83    parameter DQS_WIDTH             = 9,
  84    parameter HIGH_PERFORMANCE_MODE = "TRUE",
  85    parameter ODT_WIDTH             = 1,
  86    parameter ROW_WIDTH             = 14,
  87    parameter APPDATA_WIDTH         = 144,
  88    parameter ADDITIVE_LAT          = 0,
  89    parameter BURST_LEN             = 4,
  90    parameter BURST_TYPE            = 0,
  91    parameter CAS_LAT               = 5,
  92    parameter ECC_ENABLE            = 0,
  93    parameter MULTI_BANK_EN         = 1,
  94    parameter TWO_T_TIME_EN         = 0,
  95    parameter ODT_TYPE              = 1,
  96    parameter DDR_TYPE              = 1,
  97    parameter REDUCE_DRV            = 0,
  98    parameter REG_ENABLE            = 1,
  99    parameter TREFI_NS              = 7800,
 100    parameter TRAS                  = 40000,
 101    parameter TRCD                  = 15000,
 102    parameter TRFC                  = 105000,
 103    parameter TRP                   = 15000,
 104    parameter TRTP                  = 7500,
 105    parameter TWR                   = 15000,
 106    parameter TWTR                  = 10000,
 107    parameter CLK_PERIOD            = 3000,
 108    parameter SIM_ONLY              = 0,
 109    parameter DEBUG_EN              = 0,
 110    parameter DQS_IO_COL            = 0,
 111    parameter DQ_IO_MS              = 0
 112    )
 113   (
 114    input                                    clk0,
 115    input                                    clk90,
 116    input                                    clkdiv0,
 117    input                                    rst0,
 118    input                                    rst90,
 119    input                                    rstdiv0,
 120    input [2:0]                              app_af_cmd,
 121    input [30:0]                             app_af_addr,
 122    input                                    app_af_wren,
 123    input                                    app_wdf_wren,
 124    input [APPDATA_WIDTH-1:0]                app_wdf_data,
 125    input [(APPDATA_WIDTH/8)-1:0]            app_wdf_mask_data,
 126    output [1:0]                             rd_ecc_error,
 127    output                                   app_af_afull,
 128    output                                   app_wdf_afull,
 129    output                                   rd_data_valid,
 130    output [APPDATA_WIDTH-1:0]               rd_data_fifo_out,
 131    output                                   phy_init_done,
 132    output [CLK_WIDTH-1:0]                   ddr_ck,
 133    output [CLK_WIDTH-1:0]                   ddr_ck_n,
 134    output [ROW_WIDTH-1:0]                   ddr_addr,
 135    output [BANK_WIDTH-1:0]                  ddr_ba,
 136    output                                   ddr_ras_n,
 137    output                                   ddr_cas_n,
 138    output                                   ddr_we_n,
 139    output [CS_WIDTH-1:0]                    ddr_cs_n,
 140    output [CKE_WIDTH-1:0]                   ddr_cke,
 141    output [ODT_WIDTH-1:0]                   ddr_odt,
 142    output [DM_WIDTH-1:0]                    ddr_dm,
 143    inout [DQS_WIDTH-1:0]                    ddr_dqs,
 144    inout [DQS_WIDTH-1:0]                    ddr_dqs_n,
 145    inout [DQ_WIDTH-1:0]                     ddr_dq,
 146    // Debug signals (optional use)
 147    input                                    dbg_idel_up_all,
 148    input                                    dbg_idel_down_all,
 149    input                                    dbg_idel_up_dq,
 150    input                                    dbg_idel_down_dq,
 151    input                                    dbg_idel_up_dqs,
 152    input                                    dbg_idel_down_dqs,
 153    input                                    dbg_idel_up_gate,
 154    input                                    dbg_idel_down_gate,
 155    input [DQ_BITS-1:0]                      dbg_sel_idel_dq,
 156    input                                    dbg_sel_all_idel_dq,
 157    input [DQS_BITS:0]                       dbg_sel_idel_dqs,
 158    input                                    dbg_sel_all_idel_dqs,
 159    input [DQS_BITS:0]                       dbg_sel_idel_gate,
 160    input                                    dbg_sel_all_idel_gate,
 161    output [3:0]                             dbg_calib_done,
 162    output [3:0]                             dbg_calib_err,
 163    output [(6*DQ_WIDTH)-1:0]                dbg_calib_dq_tap_cnt,
 164    output [(6*DQS_WIDTH)-1:0]               dbg_calib_dqs_tap_cnt,
 165    output [(6*DQS_WIDTH)-1:0]               dbg_calib_gate_tap_cnt,
 166    output [DQS_WIDTH-1:0]                   dbg_calib_rd_data_sel,
 167    output [(5*DQS_WIDTH)-1:0]               dbg_calib_rden_dly,
 168    output [(5*DQS_WIDTH)-1:0]               dbg_calib_gate_dly
 169    );
 170
 171   wire [30:0]                       af_addr;
 172   wire [2:0]                        af_cmd;
 173   wire                              af_empty;
 174   wire [ROW_WIDTH-1:0]              ctrl_addr;
 175   wire                              ctrl_af_rden;
 176   wire [BANK_WIDTH-1:0]             ctrl_ba;
 177   wire                              ctrl_cas_n;
 178   wire [CS_NUM-1:0]                 ctrl_cs_n;
 179   wire                              ctrl_ras_n;
 180   wire                              ctrl_rden;
 181   wire                              ctrl_ref_flag;
 182   wire                              ctrl_we_n;
 183   wire                              ctrl_wren;
 184   wire [DQS_WIDTH-1:0]              phy_calib_rden;
 185   wire [DQS_WIDTH-1:0]              phy_calib_rden_sel;
 186   wire [DQ_WIDTH-1:0]               rd_data_fall;
 187   wire [DQ_WIDTH-1:0]               rd_data_rise;
 188   wire [(2*DQ_WIDTH)-1:0]           wdf_data;
 189   wire [((2*DQ_WIDTH)/8)-1:0]       wdf_mask_data;
 190   wire                              wdf_rden;
 191
 192   //***************************************************************************
 193
 194   ddr2_phy_top #
 195     (
 196      .BANK_WIDTH            (BANK_WIDTH),
 197      .CKE_WIDTH             (CKE_WIDTH),
 198      .CLK_WIDTH             (CLK_WIDTH),
 199      .COL_WIDTH             (COL_WIDTH),
 200      .CS_NUM                (CS_NUM),
 201      .CS_WIDTH              (CS_WIDTH),
 202      .USE_DM_PORT           (USE_DM_PORT),
 203      .DM_WIDTH              (DM_WIDTH),
 204      .DQ_WIDTH              (DQ_WIDTH),
 205      .DQ_BITS               (DQ_BITS),
 206      .DQ_PER_DQS            (DQ_PER_DQS),
 207      .DQS_BITS              (DQS_BITS),
 208      .DQS_WIDTH             (DQS_WIDTH),
 209      .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
 210      .ODT_WIDTH             (ODT_WIDTH),
 211      .ROW_WIDTH             (ROW_WIDTH),
 212      .TWO_T_TIME_EN         (TWO_T_TIME_EN),
 213      .ADDITIVE_LAT          (ADDITIVE_LAT),
 214      .BURST_LEN             (BURST_LEN),
 215      .BURST_TYPE            (BURST_TYPE),
 216      .CAS_LAT               (CAS_LAT),
 217      .ECC_ENABLE            (ECC_ENABLE),
 218      .ODT_TYPE              (ODT_TYPE),
 219      .DDR_TYPE              (DDR_TYPE),
 220      .REDUCE_DRV            (REDUCE_DRV),
 221      .REG_ENABLE            (REG_ENABLE),
 222      .TWR                   (TWR),
 223      .CLK_PERIOD            (CLK_PERIOD),
 224      .SIM_ONLY              (SIM_ONLY),
 225      .DEBUG_EN              (DEBUG_EN),
 226      .DQS_IO_COL            (DQS_IO_COL),
 227      .DQ_IO_MS              (DQ_IO_MS)
 228      )
 229     u_phy_top
 230       (
 231        .clk0                   (clk0),
 232        .clk90                  (clk90),
 233        .clkdiv0                (clkdiv0),
 234        .rst0                   (rst0),
 235        .rst90                  (rst90),
 236        .rstdiv0                (rstdiv0),
 237        .ctrl_wren              (ctrl_wren),
 238        .ctrl_addr              (ctrl_addr),
 239        .ctrl_ba                (ctrl_ba),
 240        .ctrl_ras_n             (ctrl_ras_n),
 241        .ctrl_cas_n             (ctrl_cas_n),
 242        .ctrl_we_n              (ctrl_we_n),
 243        .ctrl_cs_n              (ctrl_cs_n),
 244        .ctrl_rden              (ctrl_rden),
 245        .ctrl_ref_flag          (ctrl_ref_flag),
 246        .wdf_data               (wdf_data),
 247        .wdf_mask_data          (wdf_mask_data),
 248        .wdf_rden               (wdf_rden),
 249        .phy_init_done          (phy_init_done),
 250        .phy_calib_rden         (phy_calib_rden),
 251        .phy_calib_rden_sel     (phy_calib_rden_sel),
 252        .rd_data_rise           (rd_data_rise),
 253        .rd_data_fall           (rd_data_fall),
 254        .ddr_ck                 (ddr_ck),
 255        .ddr_ck_n               (ddr_ck_n),
 256        .ddr_addr               (ddr_addr),
 257        .ddr_ba                 (ddr_ba),
 258        .ddr_ras_n              (ddr_ras_n),
 259        .ddr_cas_n              (ddr_cas_n),
 260        .ddr_we_n               (ddr_we_n),
 261        .ddr_cs_n               (ddr_cs_n),
 262        .ddr_cke                (ddr_cke),
 263        .ddr_odt                (ddr_odt),
 264        .ddr_dm                 (ddr_dm),
 265        .ddr_dqs                (ddr_dqs),
 266        .ddr_dqs_n              (ddr_dqs_n),
 267        .ddr_dq                 (ddr_dq),
 268        .dbg_idel_up_all        (dbg_idel_up_all),
 269        .dbg_idel_down_all      (dbg_idel_down_all),
 270        .dbg_idel_up_dq         (dbg_idel_up_dq),
 271        .dbg_idel_down_dq       (dbg_idel_down_dq),
 272        .dbg_idel_up_dqs        (dbg_idel_up_dqs),
 273        .dbg_idel_down_dqs      (dbg_idel_down_dqs),
 274        .dbg_idel_up_gate       (dbg_idel_up_gate),
 275        .dbg_idel_down_gate     (dbg_idel_down_gate),
 276        .dbg_sel_idel_dq        (dbg_sel_idel_dq),
 277        .dbg_sel_all_idel_dq    (dbg_sel_all_idel_dq),
 278        .dbg_sel_idel_dqs       (dbg_sel_idel_dqs),
 279        .dbg_sel_all_idel_dqs   (dbg_sel_all_idel_dqs),
 280        .dbg_sel_idel_gate      (dbg_sel_idel_gate),
 281        .dbg_sel_all_idel_gate  (dbg_sel_all_idel_gate),
 282        .dbg_calib_done         (dbg_calib_done),
 283        .dbg_calib_err          (dbg_calib_err),
 284        .dbg_calib_dq_tap_cnt   (dbg_calib_dq_tap_cnt),
 285        .dbg_calib_dqs_tap_cnt  (dbg_calib_dqs_tap_cnt),
 286        .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
 287        .dbg_calib_rd_data_sel  (dbg_calib_rd_data_sel),
 288        .dbg_calib_rden_dly     (dbg_calib_rden_dly),
 289        .dbg_calib_gate_dly     (dbg_calib_gate_dly)
 290        );
 291
 292   ddr2_usr_top #
 293     (
 294      .BANK_WIDTH    (BANK_WIDTH),
 295      .COL_WIDTH     (COL_WIDTH),
 296      .CS_BITS       (CS_BITS),
 297      .DQ_WIDTH      (DQ_WIDTH),
 298      .DQ_PER_DQS    (DQ_PER_DQS),
 299      .DQS_WIDTH     (DQS_WIDTH),
 300      .APPDATA_WIDTH (APPDATA_WIDTH),
 301      .ECC_ENABLE    (ECC_ENABLE),
 302      .ROW_WIDTH     (ROW_WIDTH)
 303      )
 304     u_usr_top
 305       (
 306        .clk0              (clk0),
 307        .clk90             (clk90),
 308        .rst0              (rst0),
 309        .rd_data_in_rise   (rd_data_rise),
 310        .rd_data_in_fall   (rd_data_fall),
 311        .phy_calib_rden    (phy_calib_rden),
 312        .phy_calib_rden_sel(phy_calib_rden_sel),
 313        .rd_data_valid     (rd_data_valid),
 314        .rd_ecc_error      (rd_ecc_error),
 315        .rd_data_fifo_out  (rd_data_fifo_out),
 316        .app_af_cmd        (app_af_cmd),
 317        .app_af_addr       (app_af_addr),
 318        .app_af_wren       (app_af_wren),
 319        .ctrl_af_rden      (ctrl_af_rden),
 320        .af_cmd            (af_cmd),
 321        .af_addr           (af_addr),
 322        .af_empty          (af_empty),
 323        .app_af_afull      (app_af_afull),
 324        .app_wdf_wren      (app_wdf_wren),
 325        .app_wdf_data      (app_wdf_data),
 326        .app_wdf_mask_data (app_wdf_mask_data),
 327        .wdf_rden          (wdf_rden),
 328        .app_wdf_afull     (app_wdf_afull),
 329        .wdf_data          (wdf_data),
 330        .wdf_mask_data     (wdf_mask_data)
 331        );
 332
 333
 334   ddr2_ctrl #
 335     (
 336      .BANK_WIDTH    (BANK_WIDTH),
 337      .COL_WIDTH     (COL_WIDTH),
 338      .CS_BITS       (CS_BITS),
 339      .CS_NUM        (CS_NUM),
 340      .ROW_WIDTH     (ROW_WIDTH),
 341      .ADDITIVE_LAT  (ADDITIVE_LAT),
 342      .BURST_LEN     (BURST_LEN),
 343      .CAS_LAT       (CAS_LAT),
 344      .ECC_ENABLE    (ECC_ENABLE),
 345      .REG_ENABLE    (REG_ENABLE),
 346      .MULTI_BANK_EN (MULTI_BANK_EN),
 347      .TWO_T_TIME_EN (TWO_T_TIME_EN),
 348      .TREFI_NS      (TREFI_NS),
 349      .TRAS          (TRAS),
 350      .TRCD          (TRCD),
 351      .TRFC          (TRFC),
 352      .TRP           (TRP),
 353      .TRTP          (TRTP),
 354      .TWR           (TWR),
 355      .TWTR          (TWTR),
 356      .CLK_PERIOD    (CLK_PERIOD),
 357      .DDR_TYPE      (DDR_TYPE)
 358      )
 359     u_ctrl
 360       (
 361        .clk           (clk0),
 362        .rst           (rst0),
 363        .af_cmd        (af_cmd),
 364        .af_addr       (af_addr),
 365        .af_empty      (af_empty),
 366        .phy_init_done (phy_init_done),
 367        .ctrl_ref_flag (ctrl_ref_flag),
 368        .ctrl_af_rden  (ctrl_af_rden),
 369        .ctrl_wren     (ctrl_wren),
 370        .ctrl_rden     (ctrl_rden),
 371        .ctrl_addr     (ctrl_addr),
 372        .ctrl_ba       (ctrl_ba),
 373        .ctrl_ras_n    (ctrl_ras_n),
 374        .ctrl_cas_n    (ctrl_cas_n),
 375        .ctrl_we_n     (ctrl_we_n),
 376        .ctrl_cs_n     (ctrl_cs_n)
 377        );
 378
 379 endmodule