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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_phy_dq_iob.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/17 07:52:27 $
51 // \ \ / \ Date Created: Wed Aug 16 2006
57 // This module places the data in the IOBs.
60 //*****************************************************************************
64 module ddr2_phy_dq_iob #
68 parameter HIGH_PERFORMANCE_MODE = "TRUE"
103 //***************************************************************************
104 // Directed routing constraints for route between IDDR and stage 2 capture
106 // Only 2 out of the 12 wire declarations will be used for any given
107 // instantiation of this module.
109 // (1) I/O column (left, center, right) used
110 // (2) Which I/O in I/O pair (master, slave) used
111 // Nomenclature: _Xy, X = column (0 = left, 1 = center, 2 = right),
112 // y = master or slave
113 //***************************************************************************
116 (* syn_keep = "1", keep = "TRUE",
117 ROUTE = "{3;1;5vlx50tff1136;93a1e3bb!-1;-78112;-4200;S!0;-143;-1248!1;-452;0!2;2747;1575!3;2461;81!4;2732;-960!4;2732;-984!5;404;8!6;404;8!7;683;-568;L!8;843;24;L!}" *)
118 wire stg1_out_rise_0m;
119 (* syn_keep = "1", keep = "TRUE",
120 ROUTE = "{3;1;5vlx50tff1136;907923a!-1;-78112;-4192;S!0;-143;-1192!0;-143;-1272!1;-452;0!2;-452;0!3;2723;-385!4;2731;-311!5;3823;-1983!6;5209;1271!7;1394;3072!8;0;-8!9;404;8!10;0;-144!11;683;-536;L!12;404;8!14;843;8;L!}" *)
121 wire stg1_out_fall_0m;
123 (* syn_keep = "1", keep = "TRUE",
124 ROUTE = "{3;1;5vlx50tff1136;53bb9d6f!-1;-78112;-4600;S!0;-143;-712!1;-452;0!2;1008;-552!3;2780;1360!4;0;-8!5;0;-240!5;0;-264!6;404;8!7;404;8!8;683;-568;L!9;843;24;L!}" *)
125 wire stg1_out_rise_0s;
126 (* syn_keep = "1", keep = "TRUE",
127 ROUTE = "{3;1;5vlx50tff1136;46bf60d8!-1;-78112;-4592;S!0;-143;-800!1;-452;0!2;1040;1592!3;5875;-85!4;-3127;-843!4;-3127;-939!5;404;8!6;404;8!7;683;-696;L!8;843;-136;L!}" *)
128 wire stg1_out_fall_0s;
130 (* syn_keep = "1", keep = "TRUE",
131 ROUTE = "{3;1;5vlx50tff1136;9ee47800!-1;-6504;-50024;S!0;-175;-1136!1;-484;0!2;-3208;1552!3;-4160;-2092!4;-1428;1172!4;-1428;1076!5;404;8!6;404;8!7;843;-152;L!8;683;-728;L!}" *)
132 wire stg1_out_rise_1m;
133 (* syn_keep = "1", keep = "TRUE",
134 ROUTE = "{3;1;5vlx50tff1136;e7df31c2!-1;-6504;-50016;S!0;-175;-1192!1;-484;0!2;-5701;1523!3;-3095;-715!3;-4423;2421!4;0;-8!5;1328;-3288!6;0;-240!7;404;8!8;404;8!9;683;-696;L!10;843;-136;L!}" *)
135 wire stg1_out_fall_1m;
137 (* syn_keep = "1", keep = "TRUE",
138 ROUTE = "{3;1;5vlx50tff1136;a8c11eb3!-1;-6504;-50424;S!0;-175;-856!1;-484;0!2;-5677;-337!3;1033;1217!3;-295;4353!4;0;-8!5;1328;-3288!6;0;-120!7;404;8!8;404;8!9;683;-696;L!10;843;-152;L!}" *)
139 wire stg1_out_rise_1s;
140 (* syn_keep = "1", keep = "TRUE",
141 ROUTE = "{3;1;5vlx50tff1136;ed30cce!-1;-6504;-50416;S!0;-175;-848!1;-484;0!2;-3192;-432!3;-1452;1368!3;-6645;85!4;0;-8!5;5193;1035!6;0;-264!7;404;8!8;404;8!9;683;-568;L!10;843;24;L!}" *)
142 wire stg1_out_fall_1s;
144 (* syn_keep = "1", keep = "TRUE",
145 ROUTE = "{3;1;5vlx50tff1136;4d035a44!-1;54728;-108896;S!0;-175;-1248!1;-484;0!2;-3192;-424!3;-4208;2092!4;-1396;-972!4;-1396;-996!5;404;8!6;404;8!7;683;-568;L!8;843;24;L!}" *)
146 wire stg1_out_rise_2m;
147 (* syn_keep = "1", keep = "TRUE",
148 ROUTE = "{3;1;5vlx50tff1136;92ae8739!-1;54728;-108888;S!0;-175;-1272!1;-484;0!2;-5677;-329!3;-1691;-83!4;-1428;1076!4;-1428;1052!5;404;8!6;404;8!7;683;-728;L!8;843;-136;L!}" *)
149 wire stg1_out_fall_2m;
151 (* syn_keep = "1", keep = "TRUE",
152 ROUTE = "{3;1;5vlx50tff1136;9de34bf1!-1;54728;-109296;S!0;-175;-712!1;-484;0!2;-5685;-475!3;1041;1107!3;1041;1011!4;404;8!5;404;8!6;683;-536;L!7;843;24;L!}" *)
153 wire stg1_out_rise_2s;
154 (* syn_keep = "1", keep = "TRUE",
155 ROUTE = "{3;1;5vlx50tff1136;1df9e65d!-1;54728;-109288;S!0;-175;-800!1;-484;0!2;-3208;1608!3;-1436;-792!4;0;-8!5;0;-240!5;0;-144!6;404;8!7;404;8!8;843;-136;L!9;683;-696;L!}" *)
156 wire stg1_out_fall_2s;
158 //***************************************************************************
160 //***************************************************************************
170 //***************************************************************************
171 // Write (output) path
172 //***************************************************************************
174 // on a write, rising edge of DQS corresponds to rising edge of CLK180
175 // (aka falling edge of CLK0 -> rising edge DQS). We also know:
176 // 1. data must be driven 1/4 clk cycle before corresponding DQS edge
177 // 2. first rising DQS edge driven on falling edge of CLK0
178 // 3. rising data must be driven 1/4 cycle before falling edge of CLK0
179 // 4. therefore, rising data driven on rising edge of CLK
183 .DDR_CLK_EDGE("SAME_EDGE")
196 // make sure output is tri-state during reset (DQ_OE_N_R = 1)
200 .DDR_CLK_EDGE("SAME_EDGE")
213 //***************************************************************************
214 // Read data capture scheme description:
215 // Data capture consists of 3 ranks of flops, and a MUX
216 // 1. Rank 1 ("Stage 1"): IDDR captures delayed DDR DQ from memory using
218 // - Data is split into 2 SDR streams, one each for rise and fall data.
219 // - BUFIO (DQS) input inverted to IDDR. IDDR configured in SAME_EDGE
220 // mode. This means that: (1) Q1 = fall data, Q2 = rise data,
221 // (2) Both rise and fall data are output on falling edge of DQS -
222 // rather than rise output being output on one edge of DQS, and fall
223 // data on the other edge if the IDDR were configured in OPPOSITE_EDGE
224 // mode. This simplifies Stage 2 capture (only one core clock edge
225 // used, removing effects of duty-cycle-distortion), and saves one
226 // fabric flop in Rank 3.
227 // 2. Rank 2 ("Stage 2"): Fabric flops are used to capture output of first
228 // rank into FPGA clock (CLK) domain. Each rising/falling SDR stream
229 // from IDDR is feed into two flops, one clocked off rising and one off
230 // falling edge of CLK. One of these flops is chosen, with the choice
231 // being the one that reduces # of DQ/DQS taps necessary to align Stage
232 // 1 and Stage 2. Same edge is used to capture both rise and fall SDR
234 // 3. Rank 3 ("Stage 3"): Removes half-cycle paths in CLK domain from
235 // output of Rank 2. This stage, like Stage 2, is clocked by CLK. Note
236 // that Stage 3 can be expanded to also support SERDES functionality
237 // 4. Output MUX: Selects whether Stage 1 output is aligned to rising or
238 // falling edge of CLK (i.e. specifically this selects whether IDDR
239 // rise/fall output is transfered to rising or falling edge of CLK).
241 // 1. Rank 1 is implemented using an IDDR primitive
242 // 2. Rank 2 is implemented using:
243 // - An RPM to fix the location of the capture flops near the DQ I/O.
244 // The exact RPM used depends on which I/O column (left, center,
245 // right) the DQ I/O is placed at - this affects the optimal location
246 // of the slice flops (or does it - can we always choose the two
247 // columns to slices to the immediate right of the I/O to use, no
248 // matter what the column?). The origin of the RPM must be set in the
249 // UCF file using the RLOC_ORIGIN constraint (where the original is
250 // based on the DQ I/O location).
251 // - Directed Routing Constraints ("DIRT strings") to fix the routing
252 // to the rank 2 fabric flops. This is done to minimize: (1) total
253 // route delay (and therefore minimize voltage/temperature-related
254 // variations), and (2) minimize skew both within each rising and
255 // falling data net, as well as between the rising and falling nets.
256 // The exact DIRT string used depends on: (1) which I/O column the
257 // DQ I/O is placed, and (2) whether the DQ I/O is placed on the
258 // "Master" or "Slave" I/O of a diff pair (DQ is not differential, but
259 // the routing will be affected by which of each I/O pair is used)
260 // 3. Rank 3 is implemented using fabric flops. No LOC or DIRT contraints
261 // are used, tools are expected to place these and meet PERIOD timing
262 // without constraints (constraints may be necessary for "full" designs,
263 // in this case, user may need to add LOC constraints - if this is the
264 // case, there are no constraints - other than meeting PERIOD timing -
266 //***************************************************************************
268 //***************************************************************************
269 // MIG 2.2: Define AREA_GROUP = "DDR_CAPTURE_FFS" contain all RPM flops in
270 // design. In UCF file, add constraint:
271 // AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
272 // This is done to prevent MAP from packing unrelated logic into
273 // the slices used by the RPMs. Doing so may cause the DIRT strings
274 // that define the IDDR -> fabric flop routing to later become
275 // unroutable during PAR because the unrelated logic placed by MAP
276 // may use routing resources required by the DIRT strings. MAP
277 // does not currently take into account DIRT strings when placing
279 //***************************************************************************
281 // IDELAY to delay incoming data for synchronization purposes
285 .IDELAY_TYPE ("VARIABLE"),
286 .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
292 .DATAOUT (dq_idelay),
303 //***************************************************************************
304 // Rank 1 capture: Use IDDR to generate two SDR outputs
305 //***************************************************************************
307 // invert clock to IDDR in order to use SAME_EDGE mode (otherwise, we "run
308 // out of clocks" because DQS is not continuous
309 assign dq_iddr_clk = ~dqs;
311 //***************************************************************************
312 // Rank 2 capture: Use fabric flops to capture Rank 1 output. Use RPM and
313 // DIRT strings here.
314 // BEL ("Basic Element of Logic") and relative location constraints for
315 // second stage capture. C
317 // (1) I/O column (left, center, right) used
318 // (2) Which I/O in I/O pair (master, slave) used
319 //***************************************************************************
321 // Six different cases for the different I/O column, master/slave
322 // combinations (can't seem to do this using a localparam, which
323 // would be easier, XST doesn't allow it)
325 if ((DQ_MS == 1) && (DQ_COL == 0)) begin: gen_stg2_0m
327 //*****************************************************************
329 //*****************************************************************
333 .DDR_CLK_EDGE ("SAME_EDGE")
337 .Q1 (stg1_out_fall_0m),
338 .Q2 (stg1_out_rise_0m),
346 //*********************************************************
347 // Slice #1 (posedge CLK): Used for:
348 // 1. IDDR transfer to CLK0 rising edge domain ("stg2a")
349 // 2. stg2 falling edge -> stg3 rising edge transfer
350 //*********************************************************
353 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
354 AREA_GROUP = "DDR_CAPTURE_FFS" *)
355 FDRSE u_ff_stg2a_fall
360 .D (stg1_out_fall_0m),
365 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
366 AREA_GROUP = "DDR_CAPTURE_FFS" *)
367 FDRSE u_ff_stg2a_rise
372 .D (stg1_out_rise_0m),
377 // Stage 3 falling -> rising edge translation
378 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
379 AREA_GROUP = "DDR_CAPTURE_FFS" *)
380 FDRSE u_ff_stg3b_fall
390 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
391 AREA_GROUP = "DDR_CAPTURE_FFS" *)
392 FDRSE u_ff_stg3b_rise
403 //*********************************************************
404 // Slice #2 (posedge CLK): Used for:
405 // 1. IDDR transfer to CLK0 falling edge domain ("stg2b")
406 //*********************************************************
408 (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "DFF",
409 AREA_GROUP = "DDR_CAPTURE_FFS" *)
410 FDRSE_1 u_ff_stg2b_fall
415 .D (stg1_out_fall_0m),
421 (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
422 AREA_GROUP = "DDR_CAPTURE_FFS" *)
423 FDRSE_1 u_ff_stg2b_rise
428 .D (stg1_out_rise_0m),
434 end else if ((DQ_MS == 0) && (DQ_COL == 0)) begin: gen_stg2_0s
436 //*****************************************************************
438 //*****************************************************************
442 .DDR_CLK_EDGE ("SAME_EDGE")
446 .Q1 (stg1_out_fall_0s),
447 .Q2 (stg1_out_rise_0s),
455 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "BFF",
456 AREA_GROUP = "DDR_CAPTURE_FFS" *)
457 FDRSE u_ff_stg2a_fall
462 .D (stg1_out_fall_0s),
467 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
468 AREA_GROUP = "DDR_CAPTURE_FFS" *)
469 FDRSE u_ff_stg2a_rise
474 .D (stg1_out_rise_0s),
480 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
481 AREA_GROUP = "DDR_CAPTURE_FFS" *)
482 FDRSE u_ff_stg3b_fall
492 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
493 AREA_GROUP = "DDR_CAPTURE_FFS" *)
494 FDRSE u_ff_stg3b_rise
505 (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
506 AREA_GROUP = "DDR_CAPTURE_FFS" *)
507 FDRSE_1 u_ff_stg2b_fall
512 .D (stg1_out_fall_0s),
517 (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "CFF",
518 AREA_GROUP = "DDR_CAPTURE_FFS" *)
519 FDRSE_1 u_ff_stg2b_rise
524 .D (stg1_out_rise_0s),
530 end else if ((DQ_MS == 1) && (DQ_COL == 1)) begin: gen_stg2_1m
532 //*****************************************************************
534 //*****************************************************************
538 .DDR_CLK_EDGE ("SAME_EDGE")
542 .Q1 (stg1_out_fall_1m),
543 .Q2 (stg1_out_rise_1m),
551 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "BFF",
552 AREA_GROUP = "DDR_CAPTURE_FFS" *)
553 FDRSE u_ff_stg2a_fall
558 .D (stg1_out_fall_1m),
563 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
564 AREA_GROUP = "DDR_CAPTURE_FFS" *)
565 FDRSE u_ff_stg2a_rise
570 .D (stg1_out_rise_1m),
576 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
577 AREA_GROUP = "DDR_CAPTURE_FFS" *)
578 FDRSE u_ff_stg3b_fall
588 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
589 AREA_GROUP = "DDR_CAPTURE_FFS" *)
590 FDRSE u_ff_stg3b_rise
601 (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
602 AREA_GROUP = "DDR_CAPTURE_FFS" *)
603 FDRSE_1 u_ff_stg2b_fall
608 .D (stg1_out_fall_1m),
613 (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "BFF",
614 AREA_GROUP = "DDR_CAPTURE_FFS" *)
615 FDRSE_1 u_ff_stg2b_rise
620 .D (stg1_out_rise_1m),
626 end else if ((DQ_MS == 0) && (DQ_COL == 1)) begin: gen_stg2_1s
628 //*****************************************************************
630 //*****************************************************************
634 .DDR_CLK_EDGE ("SAME_EDGE")
638 .Q1 (stg1_out_fall_1s),
639 .Q2 (stg1_out_rise_1s),
647 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
648 AREA_GROUP = "DDR_CAPTURE_FFS" *)
649 FDRSE u_ff_stg2a_fall
654 .D (stg1_out_fall_1s),
659 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
660 AREA_GROUP = "DDR_CAPTURE_FFS" *)
661 FDRSE u_ff_stg2a_rise
666 .D (stg1_out_rise_1s),
672 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
673 AREA_GROUP = "DDR_CAPTURE_FFS" *)
674 FDRSE u_ff_stg3b_fall
684 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
685 AREA_GROUP = "DDR_CAPTURE_FFS" *)
686 FDRSE u_ff_stg3b_rise
697 (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
698 AREA_GROUP = "DDR_CAPTURE_FFS" *)
699 FDRSE_1 u_ff_stg2b_fall
704 .D (stg1_out_fall_1s),
709 (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "BFF",
710 AREA_GROUP = "DDR_CAPTURE_FFS" *)
711 FDRSE_1 u_ff_stg2b_rise
716 .D (stg1_out_rise_1s),
722 end else if ((DQ_MS == 1) && (DQ_COL == 2)) begin: gen_stg2_2m
724 //*****************************************************************
726 //*****************************************************************
730 .DDR_CLK_EDGE ("SAME_EDGE")
734 .Q1 (stg1_out_fall_2m),
735 .Q2 (stg1_out_rise_2m),
743 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
744 AREA_GROUP = "DDR_CAPTURE_FFS" *)
745 FDRSE u_ff_stg2a_fall
750 .D (stg1_out_fall_2m),
755 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
756 AREA_GROUP = "DDR_CAPTURE_FFS" *)
757 FDRSE u_ff_stg2a_rise
762 .D (stg1_out_rise_2m),
768 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
769 AREA_GROUP = "DDR_CAPTURE_FFS" *)
770 FDRSE u_ff_stg3b_fall
780 (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "BFF",
781 AREA_GROUP = "DDR_CAPTURE_FFS" *)
782 FDRSE u_ff_stg3b_rise
793 (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
794 AREA_GROUP = "DDR_CAPTURE_FFS" *)
795 FDRSE_1 u_ff_stg2b_fall
800 .D (stg1_out_fall_2m),
805 (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "CFF",
806 AREA_GROUP = "DDR_CAPTURE_FFS" *)
807 FDRSE_1 u_ff_stg2b_rise
812 .D (stg1_out_rise_2m),
818 end else if ((DQ_MS == 0) && (DQ_COL == 2)) begin: gen_stg2_2s
820 //*****************************************************************
822 //*****************************************************************
826 .DDR_CLK_EDGE ("SAME_EDGE")
830 .Q1 (stg1_out_fall_2s),
831 .Q2 (stg1_out_rise_2s),
839 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
840 AREA_GROUP = "DDR_CAPTURE_FFS" *)
841 FDRSE u_ff_stg2a_fall
846 .D (stg1_out_fall_2s),
851 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
852 AREA_GROUP = "DDR_CAPTURE_FFS" *)
853 FDRSE u_ff_stg2a_rise
858 .D (stg1_out_rise_2s),
863 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
864 AREA_GROUP = "DDR_CAPTURE_FFS" *)
865 FDRSE u_ff_stg3b_fall
875 (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
876 AREA_GROUP = "DDR_CAPTURE_FFS" *)
877 FDRSE u_ff_stg3b_rise
888 (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "AFF",
889 AREA_GROUP = "DDR_CAPTURE_FFS" *)
890 FDRSE_1 u_ff_stg2b_fall
895 .D (stg1_out_fall_2s),
900 (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
901 AREA_GROUP = "DDR_CAPTURE_FFS" *)
902 FDRSE_1 u_ff_stg2b_rise
907 .D (stg1_out_rise_2s),
916 //***************************************************************************
917 // Second stage flops clocked by posedge CLK0 don't need another layer of
919 //***************************************************************************
921 assign stg3a_out_rise = stg2a_out_rise;
922 assign stg3a_out_fall = stg2a_out_fall;
924 //*******************************************************************
926 assign rd_data_rise = (rd_data_sel) ? stg3a_out_rise : stg3b_out_rise;
927 assign rd_data_fall = (rd_data_sel) ? stg3a_out_fall : stg3b_out_fall;