1 //*****************************************************************************
2 // DISCLAIMER OF LIABILITY
4 // This text/file contains proprietary, confidential
5 // information of Xilinx, Inc., is distributed under license
6 // from Xilinx, Inc., and may be used, copied and/or
7 // disclosed only pursuant to the terms of a valid license
8 // agreement with Xilinx, Inc. Xilinx hereby grants you a
9 // license to use this text/file solely for design, simulation,
10 // implementation and creation of design files limited
11 // to Xilinx devices or technologies. Use with non-Xilinx
12 // devices or technologies is expressly prohibited and
13 // immediately terminates your license unless covered by
14 // a separate agreement.
16 // Xilinx is providing this design, code, or information
17 // "as-is" solely for use in developing programs and
18 // solutions for Xilinx devices, with no obligation on the
19 // part of Xilinx to provide support. By providing this design,
20 // code, or information as one possible implementation of
21 // this feature, application or standard, Xilinx is making no
22 // representation that this implementation is free from any
23 // claims of infringement. You are responsible for
24 // obtaining any rights you may require for your implementation.
25 // Xilinx expressly disclaims any warranty whatsoever with
26 // respect to the adequacy of the implementation, including
27 // but not limited to any warranties or representations that this
28 // implementation is free from claims of infringement, implied
29 // warranties of merchantability or fitness for a particular
32 // Xilinx products are not intended for use in life support
33 // appliances, devices, or systems. Use in such applications is
34 // expressly prohibited.
36 // Any modifications that are made to the Source Code are
37 // done at the users sole risk and will be unsupported.
39 // Copyright (c) 2006-2007 Xilinx, Inc. All rights reserved.
41 // This copyright and support notice must be retained as part
42 // of this text at all times.
43 //*****************************************************************************
46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_phy_dqs_iob.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/22 15:41:06 $
51 // \ \ / \ Date Created: Wed Aug 16 2006
57 // This module places the data strobes in the IOBs.
60 //*****************************************************************************
64 module ddr2_phy_dqs_iob #
66 parameter DDR_TYPE = 1,
67 parameter HIGH_PERFORMANCE_MODE = "TRUE"
96 reg dqs_rst_n_r /* */;
98 wire en_dqs_sync /* synthesis syn_keep = 1 */;
100 // for simulation only. Synthesis should ignore this delay
101 localparam DQS_NET_DELAY = 0.8;
103 assign clk180 = ~clk0;
105 // add delta delay to inputs clocked by clk180 to avoid delta-delay
107 assign dqs_rst_n_delay = dqs_rst_n;
108 assign dqs_oe_n_delay = dqs_oe_n;
110 //***************************************************************************
111 // DQS input-side resources:
112 // - IODELAY (pad -> IDELAY)
113 // - BUFIO (IDELAY -> BUFIO)
114 //***************************************************************************
116 // Route DQS from PAD to IDELAY
120 .IDELAY_TYPE("VARIABLE"),
121 .HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
127 .DATAOUT (dqs_idelay),
138 // From IDELAY to BUFIO
145 // To model additional delay of DQS BUFIO + gating network
146 // for behavioral simulation. Make sure to select a delay number smaller
147 // than half clock cycle (otherwise output will not track input changes
148 // because of inertial delay). Duplicate to avoid delta delay issues.
149 assign #(DQS_NET_DELAY) i_delayed_dqs = dqs_bufio;
150 assign #(DQS_NET_DELAY) delayed_dqs = dqs_bufio;
152 //***************************************************************************
153 // DQS gate circuit (not supported for all controllers)
154 //***************************************************************************
157 // en_dqs -> IDELAY -> en_dqs_sync -> IDDR.S -> dq_ce ->
160 // Delay CE control so that it's in phase with delayed DQS
163 .DELAY_SRC ("DATAIN"),
164 .IDELAY_TYPE ("VARIABLE"),
165 .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
171 .DATAOUT (en_dqs_sync),
182 // Generate sync'ed CE to DQ IDDR's using an IDDR clocked by DQS
183 // We could also instantiate a negative-edge SDR flop here
186 .DDR_CLK_EDGE ("OPPOSITE_EDGE"),
194 .Q2 (dq_ce), // output on falling edge
202 //***************************************************************************
203 // DQS output-side resources
204 //***************************************************************************
206 // synthesis attribute keep of dqs_rst_n_r is "true"
207 always @(posedge clk180)
208 dqs_rst_n_r <= dqs_rst_n_delay;
213 .DDR_CLK_EDGE("OPPOSITE_EDGE")
220 .D1 (dqs_rst_n_r), // keep output deasserted for write preamble
226 (* IOB = "TRUE" *) FDP u_tri_state_dqs
234 //***************************************************************************
236 // use either single-ended (for DDR1) or differential (for DDR2) DQS input
239 if (DDR_TYPE > 0) begin: gen_dqs_iob_ddr2
248 end else begin: gen_dqs_iob_ddr1