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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_phy_init.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/22 15:41:06 $
51 // \ \ / \ Date Created: Thu Aug 24 2006
58 // This module is the intialization control logic of the memory interface.
59 // All commands are issued from here acoording to the burst, CAS Latency and
62 //*****************************************************************************
66 module ddr2_phy_init #
68 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
69 // board design). Actual values may be different. Actual parameters values
70 // are passed from design top module ddr2_sdram module. Please refer to
71 // the ddr2_sdram module for actual values.
72 parameter BANK_WIDTH = 2,
73 parameter CKE_WIDTH = 1,
74 parameter COL_WIDTH = 10,
76 parameter DQ_WIDTH = 72,
77 parameter ODT_WIDTH = 1,
78 parameter ROW_WIDTH = 14,
79 parameter ADDITIVE_LAT = 0,
80 parameter BURST_LEN = 4,
81 parameter TWO_T_TIME_EN = 0,
82 parameter BURST_TYPE = 0,
83 parameter CAS_LAT = 5,
84 parameter ODT_TYPE = 1,
85 parameter REDUCE_DRV = 0,
86 parameter REG_ENABLE = 1,
87 parameter TWR = 15000,
88 parameter CLK_PERIOD = 3000,
89 parameter DDR_TYPE = 1,
90 parameter SIM_ONLY = 0
97 input [3:0] calib_done,
100 output reg [3:0] calib_start,
101 output reg calib_ref_done,
102 output reg phy_init_wren,
103 output reg phy_init_rden,
104 output [ROW_WIDTH-1:0] phy_init_addr,
105 output [BANK_WIDTH-1:0] phy_init_ba,
106 output phy_init_ras_n,
107 output phy_init_cas_n,
108 output phy_init_we_n,
109 output [CS_NUM-1:0] phy_init_cs_n,
110 output [CKE_WIDTH-1:0] phy_init_cke,
111 output reg phy_init_done,
112 output phy_init_data_sel
115 // time to wait between consecutive commands in PHY_INIT - this is a
116 // generic number, and must be large enough to account for worst case
117 // timing parameter (tRFC - refresh-to-active) across all memory speed
118 // grades and operating frequencies. Expressed in CLKDIV clock cycles.
119 localparam CNTNEXT_CMD = 7'b1111111;
120 // time to wait between read and read or precharge for stage 3 & 4
121 // the larger CNTNEXT_CMD can also be used, use smaller number to
122 // speed up calibration - avoid tRAS violation, and speeds up simulation
123 localparam CNTNEXT_RD = 4'b1111;
125 // Write recovery (WR) time - is defined by
126 // tWR (in nanoseconds) by tCK (in nanoseconds) and rounding up a
127 // noninteger value to the next integer
128 localparam integer WR_RECOVERY = ((TWR + CLK_PERIOD) - 1)/CLK_PERIOD;
130 localparam INIT_CAL1_READ = 5'h00;
131 localparam INIT_CAL2_READ = 5'h01;
132 localparam INIT_CAL3_READ = 5'h02;
133 localparam INIT_CAL4_READ = 5'h03;
134 localparam INIT_CAL1_WRITE = 5'h04;
135 localparam INIT_CAL2_WRITE = 5'h05;
136 localparam INIT_CAL3_WRITE = 5'h06;
137 localparam INIT_DUMMY_ACTIVE_WAIT = 5'h07;
138 localparam INIT_PRECHARGE = 5'h08;
139 localparam INIT_LOAD_MODE = 5'h09;
140 localparam INIT_AUTO_REFRESH = 5'h0A;
141 localparam INIT_IDLE = 5'h0B;
142 localparam INIT_CNT_200 = 5'h0C;
143 localparam INIT_CNT_200_WAIT = 5'h0D;
144 localparam INIT_PRECHARGE_WAIT = 5'h0E;
145 localparam INIT_MODE_REGISTER_WAIT = 5'h0F;
146 localparam INIT_AUTO_REFRESH_WAIT = 5'h10;
147 localparam INIT_DEEP_MEMORY_ST = 5'h11;
148 localparam INIT_DUMMY_ACTIVE = 5'h12;
149 localparam INIT_CAL1_WRITE_READ = 5'h13;
150 localparam INIT_CAL1_READ_WAIT = 5'h14;
151 localparam INIT_CAL2_WRITE_READ = 5'h15;
152 localparam INIT_CAL2_READ_WAIT = 5'h16;
153 localparam INIT_CAL3_WRITE_READ = 5'h17;
154 localparam INIT_CAL3_READ_WAIT = 5'h18;
155 localparam INIT_CAL4_READ_WAIT = 5'h19;
156 localparam INIT_CALIB_REF = 5'h1A;
157 localparam INIT_ZQCL = 5'h1B;
158 localparam INIT_WAIT_DLLK_ZQINIT = 5'h1C;
160 localparam INIT_CNTR_INIT = 4'h0;
161 localparam INIT_CNTR_PRECH_1 = 4'h1;
162 localparam INIT_CNTR_EMR2_INIT = 4'h2;
163 localparam INIT_CNTR_EMR3_INIT = 4'h3;
164 localparam INIT_CNTR_EMR_EN_DLL = 4'h4;
165 localparam INIT_CNTR_MR_RST_DLL = 4'h5;
166 localparam INIT_CNTR_CNT_200_WAIT = 4'h6;
167 localparam INIT_CNTR_PRECH_2 = 4'h7;
168 localparam INIT_CNTR_AR_1 = 4'h8;
169 localparam INIT_CNTR_AR_2 = 4'h9;
170 localparam INIT_CNTR_MR_ACT_DLL = 4'hA;
171 localparam INIT_CNTR_EMR_DEF_OCD = 4'hB;
172 localparam INIT_CNTR_EMR_EXIT_OCD = 4'hC;
173 localparam INIT_CNTR_DEEP_MEM = 4'hD;
174 localparam INIT_CNTR_PRECH_3 = 4'hE;
175 localparam INIT_CNTR_DONE = 4'hF;
182 reg [1:0] burst_addr_r;
183 reg [1:0] burst_cnt_r;
184 wire [1:0] burst_val;
191 reg [3:0] calib_done_r;
192 reg calib_ref_req_posedge;
194 reg [15:0] calib_start_shift0_r;
195 reg [15:0] calib_start_shift1_r;
196 reg [15:0] calib_start_shift2_r;
197 reg [15:0] calib_start_shift3_r;
198 reg [1:0] chip_cnt_r;
199 reg [4:0] cke_200us_cnt_r;
200 reg cke_200us_cnt_en_r;
201 reg [7:0] cnt_200_cycle_r;
202 reg cnt_200_cycle_done_r;
209 reg [ROW_WIDTH-1:0] ddr_addr_r;
210 reg [ROW_WIDTH-1:0] ddr_addr_r1;
211 reg [BANK_WIDTH-1:0] ddr_ba_r;
212 reg [BANK_WIDTH-1:0] ddr_ba_r1;
215 reg [CKE_WIDTH-1:0] ddr_cke_r;
216 reg [CS_NUM-1:0] ddr_cs_n_r;
217 reg [CS_NUM-1:0] ddr_cs_n_r1;
218 reg [CS_NUM-1:0] ddr_cs_disable_r;
223 wire [15:0] ext_mode_reg;
224 reg [3:0] init_cnt_r;
226 reg [4:0] init_next_state;
227 reg [4:0] init_state_r;
228 reg [4:0] init_state_r1;
229 reg [4:0] init_state_r2;
230 wire [15:0] load_mode_reg;
231 wire [15:0] load_mode_reg0;
232 wire [15:0] load_mode_reg1;
233 wire [15:0] load_mode_reg2;
234 wire [15:0] load_mode_reg3;
236 reg phy_init_done_r1;
237 reg phy_init_done_r2;
238 reg phy_init_done_r3;
240 wire [3:0] start_cal;
242 //***************************************************************************
244 //*****************************************************************
245 // DDR1 and DDR2 Load mode register
246 // Mode Register (MR):
247 // [15:14] - unused - 00
248 // [13] - reserved - 0
249 // [12] - Power-down mode - 0 (normal)
250 // [11:9] - write recovery - for Auto Precharge (tWR/tCK)
251 // [8] - DLL reset - 0 or 1
252 // [7] - Test Mode - 0 (normal)
253 // [6:4] - CAS latency - CAS_LAT
254 // [3] - Burst Type - BURST_TYPE
255 // [2:0] - Burst Length - BURST_LEN
256 //*****************************************************************
259 if (DDR_TYPE == DDR2) begin: gen_load_mode_reg_ddr2
260 assign load_mode_reg[2:0] = (BURST_LEN == 8) ? 3'b011 :
261 ((BURST_LEN == 4) ? 3'b010 : 3'b111);
262 assign load_mode_reg[3] = BURST_TYPE;
263 assign load_mode_reg[6:4] = (CAS_LAT == 3) ? 3'b011 :
264 ((CAS_LAT == 4) ? 3'b100 :
265 ((CAS_LAT == 5) ? 3'b101 : 3'b111));
266 assign load_mode_reg[7] = 1'b0;
267 assign load_mode_reg[8] = 1'b0; // init value only (DLL not reset)
268 assign load_mode_reg[11:9] = (WR_RECOVERY == 6) ? 3'b101 :
269 ((WR_RECOVERY == 5) ? 3'b100 :
270 ((WR_RECOVERY == 4) ? 3'b011 :
271 ((WR_RECOVERY == 3) ? 3'b010 :
273 assign load_mode_reg[15:12] = 4'b000;
274 end else if (DDR_TYPE == DDR1)begin: gen_load_mode_reg_ddr1
275 assign load_mode_reg[2:0] = (BURST_LEN == 8) ? 3'b011 :
276 ((BURST_LEN == 4) ? 3'b010 :
277 ((BURST_LEN == 2) ? 3'b001 : 3'b111));
278 assign load_mode_reg[3] = BURST_TYPE;
279 assign load_mode_reg[6:4] = (CAS_LAT == 2) ? 3'b010 :
280 ((CAS_LAT == 3) ? 3'b011 :
281 ((CAS_LAT == 25) ? 3'b110 : 3'b111));
282 assign load_mode_reg[12:7] = 6'b000000; // init value only
283 assign load_mode_reg[15:13] = 3'b000;
287 //*****************************************************************
288 // DDR1 and DDR2 ext mode register
289 // Extended Mode Register (MR):
290 // [15:14] - unused - 00
291 // [13] - reserved - 0
292 // [12] - output enable - 0 (enabled)
293 // [11] - RDQS enable - 0 (disabled)
294 // [10] - DQS# enable - 0 (enabled)
295 // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)
296 // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
297 // [5:3] - Additive CAS - ADDITIVE_CAS
299 // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)
300 // [0] - DLL enable - 0 (normal)
301 //*****************************************************************
304 if (DDR_TYPE == DDR2) begin: gen_ext_mode_reg_ddr2
305 assign ext_mode_reg[0] = 1'b0;
306 assign ext_mode_reg[1] = REDUCE_DRV;
307 assign ext_mode_reg[2] = ((ODT_TYPE == 1) || (ODT_TYPE == 3)) ?
309 assign ext_mode_reg[5:3] = (ADDITIVE_LAT == 0) ? 3'b000 :
310 ((ADDITIVE_LAT == 1) ? 3'b001 :
311 ((ADDITIVE_LAT == 2) ? 3'b010 :
312 ((ADDITIVE_LAT == 3) ? 3'b011 :
313 ((ADDITIVE_LAT == 4) ? 3'b100 :
315 assign ext_mode_reg[6] = ((ODT_TYPE == 2) || (ODT_TYPE == 3)) ?
317 assign ext_mode_reg[9:7] = 3'b000;
318 assign ext_mode_reg[10] = 1'b0;
319 assign ext_mode_reg[15:10] = 6'b000000;
320 end else if (DDR_TYPE == DDR1)begin: gen_ext_mode_reg_ddr1
321 assign ext_mode_reg[0] = 1'b0;
322 assign ext_mode_reg[1] = REDUCE_DRV;
323 assign ext_mode_reg[12:2] = 11'b00000000000;
324 assign ext_mode_reg[15:13] = 3'b000;
328 //*****************************************************************
329 // DDR3 Load mode reg0
330 // Mode Register (MR0):
331 // [15:13] - unused - 000
332 // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
333 // 1 (DLL maintained)
334 // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)
335 // [8] - DLL reset - 0 or 1
336 // [7] - Test Mode - 0 (normal)
337 // [6:4],[2] - CAS latency - CAS_LAT
338 // [3] - Burst Type - BURST_TYPE
339 // [1:0] - Burst Length - BURST_LEN
340 //*****************************************************************
343 if (DDR_TYPE == DDR3) begin: gen_load_mode_reg0_ddr3
344 assign load_mode_reg0[1:0] = (BURST_LEN == 8) ? 2'b00 :
345 ((BURST_LEN == 4) ? 2'b10 : 2'b11);
346 // Part of CAS latency. This bit is '0' for all CAS latencies
347 assign load_mode_reg0[2] = 1'b0;
348 assign load_mode_reg0[3] = BURST_TYPE;
349 assign load_mode_reg0[6:4] = (CAS_LAT == 5) ? 3'b001 :
350 (CAS_LAT == 6) ? 3'b010 : 3'b111;
351 assign load_mode_reg0[7] = 1'b0;
352 // init value only (DLL reset)
353 assign load_mode_reg0[8] = 1'b1;
354 assign load_mode_reg0[11:9] = 3'b010;
355 // Precharge Power-Down DLL 'slow-exit'
356 assign load_mode_reg0[12] = 1'b0;
357 assign load_mode_reg0[15:13] = 3'b000;
361 //*****************************************************************
362 // DDR3 Load mode reg1
363 // Mode Register (MR1):
364 // [15:13] - unused - 00
365 // [12] - output enable - 0 (enabled for DQ, DQS, DQS#)
366 // [11] - TDQS enable - 0 (TDQS disabled and DM enabled)
367 // [10] - reserved - 0 (must be '0')
369 // [8] - reserved - 0 (must be '0')
370 // [7] - write leveling - 0 (disabled), 1 (enabled)
371 // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
372 // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
373 // [4:3] - Additive CAS - ADDITIVE_CAS
375 // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
376 // [0] - DLL enable - 0 (normal)
377 //*****************************************************************
380 if (DDR_TYPE == DDR3) begin: gen_ext_mode_reg1_ddr3
381 // DLL enabled during Imitialization
382 assign load_mode_reg1[0] = 1'b0;
384 assign load_mode_reg1[1] = REDUCE_DRV;
385 assign load_mode_reg1[2] = ((ODT_TYPE == 1) || (ODT_TYPE == 3)) ?
387 assign load_mode_reg1[4:3] = (ADDITIVE_LAT == 0) ? 2'b00 :
388 ((ADDITIVE_LAT == 1) ? 2'b01 :
389 ((ADDITIVE_LAT == 2) ? 2'b10 :
392 assign load_mode_reg1[5] = 1'b0;
393 assign load_mode_reg1[6] = ((ODT_TYPE == 2) || (ODT_TYPE == 3)) ?
395 // Make zero WRITE_LEVEL
396 assign load_mode_reg1[7] = 0;
397 assign load_mode_reg1[8] = 1'b0;
398 assign load_mode_reg1[9] = 1'b0;
399 assign load_mode_reg1[10] = 1'b0;
400 assign load_mode_reg1[15:11] = 5'b00000;
404 //*****************************************************************
405 // DDR3 Load mode reg2
406 // Mode Register (MR2):
407 // [15:11] - unused - 00
408 // [10:9] - RTT_WR - 00 (Dynamic ODT off)
409 // [8] - reserved - 0 (must be '0')
410 // [7] - self-refresh temperature range -
411 // 0 (normal), 1 (extended)
412 // [6] - Auto Self-Refresh - 0 (manual), 1(auto)
413 // [5:3] - CAS Write Latency (CWL) -
414 // 000 (5 for 400 MHz device),
415 // 001 (6 for 400 MHz to 533 MHz devices),
416 // 010 (7 for 533 MHz to 667 MHz devices),
417 // 011 (8 for 667 MHz to 800 MHz)
418 // [2:0] - Partial Array Self-Refresh (Optional) -
420 //*****************************************************************
423 if (DDR_TYPE == DDR3) begin: gen_ext_mode_reg2_ddr3
424 assign load_mode_reg2[2:0] = 3'b000;
425 assign load_mode_reg2[5:3] = (CAS_LAT == 5) ? 3'b000 :
426 (CAS_LAT == 6) ? 3'b001 : 3'b111;
427 assign load_mode_reg2[6] = 1'b0; // Manual Self-Refresh
428 assign load_mode_reg2[7] = 1'b0;
429 assign load_mode_reg2[8] = 1'b0;
430 assign load_mode_reg2[10:9] = 2'b00;
431 assign load_mode_reg2[15:11] = 5'b00000;
435 //*****************************************************************
436 // DDR3 Load mode reg3
437 // Mode Register (MR3):
438 // [15:3] - unused - All zeros
439 // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)
440 // [1:0] - MPR location - 00 (Predefined pattern)
441 //*****************************************************************
444 if (DDR_TYPE == DDR3)begin: gen_ext_mode_reg3_ddr3
445 assign load_mode_reg3[1:0] = 2'b00;
446 assign load_mode_reg3[2] = 1'b0;
447 assign load_mode_reg3[15:3] = 13'b0000000000000;
451 //***************************************************************************
452 // Logic for calibration start, and for auto-refresh during cal request
453 // CALIB_REF_REQ is used by calibration logic to request auto-refresh
454 // durign calibration (used to avoid tRAS violation is certain calibration
455 // stages take a long time). Once the auto-refresh is complete and cal can
456 // be resumed, CALIB_REF_DONE is asserted by PHY_INIT.
457 //***************************************************************************
459 // generate pulse for each of calibration start controls
460 assign start_cal[0] = ((init_state_r1 == INIT_CAL1_READ) &&
461 (init_state_r2 != INIT_CAL1_READ));
462 assign start_cal[1] = ((init_state_r1 == INIT_CAL2_READ) &&
463 (init_state_r2 != INIT_CAL2_READ));
464 assign start_cal[2] = ((init_state_r1 == INIT_CAL3_READ) &&
465 (init_state_r2 == INIT_CAL3_WRITE_READ));
466 assign start_cal[3] = ((init_state_r1 == INIT_CAL4_READ) &&
467 (init_state_r2 == INIT_DUMMY_ACTIVE_WAIT));
469 // Generate positive-edge triggered, latched signal to force initialization
470 // to pause calibration, and to issue auto-refresh. Clear flag as soon as
472 always @(posedge clkdiv0)
474 calib_ref_req_r <= 1'b0;
475 calib_ref_req_posedge <= 1'b0;
478 calib_ref_req_r <= calib_ref_req;
479 calib_ref_req_posedge <= calib_ref_req & ~calib_ref_req_r;
480 if (init_state_r1 == INIT_AUTO_REFRESH)
482 else if (calib_ref_req_posedge)
486 // flag to tell cal1 calibration was started.
487 // This flag is used for cal1 auto refreshes
488 // some of these bits may not be needed - only needed for those stages that
489 // need refreshes within the stage (i.e. very long stages)
490 always @(posedge clkdiv0)
492 cal1_started_r <= 1'b0;
493 cal2_started_r <= 1'b0;
494 cal4_started_r <= 1'b0;
497 cal1_started_r <= 1'b1;
499 cal2_started_r <= 1'b1;
501 cal4_started_r <= 1'b1;
504 // Delay start of each calibration by 16 clock cycles to
505 // ensure that when calibration logic begins, that read data is already
506 // appearing on the bus. Don't really need it, it's more for simulation
507 // purposes. Each circuit should synthesize using an SRL16.
508 // In first stage of calibration periodic auto refreshes
509 // will be issued to meet memory timing. calib_start_shift0_r[15] will be
510 // asserted more than once.calib_start[0] is anded with cal1_started_r so
511 // that it is asserted only once. cal1_refresh_done is anded with
512 // cal1_started_r so that it is asserted after the auto refreshes.
513 always @(posedge clkdiv0) begin
514 calib_start_shift0_r <= {calib_start_shift0_r[14:0], start_cal[0]};
515 calib_start_shift1_r <= {calib_start_shift1_r[14:0], start_cal[1]};
516 calib_start_shift2_r <= {calib_start_shift2_r[14:0], start_cal[2]};
517 calib_start_shift3_r <= {calib_start_shift3_r[14:0], start_cal[3]};
518 calib_start[0] <= calib_start_shift0_r[15] & ~cal1_started_r;
519 calib_start[1] <= calib_start_shift1_r[15] & ~cal2_started_r;
520 calib_start[2] <= calib_start_shift2_r[15];
521 calib_start[3] <= calib_start_shift3_r[15] & ~cal4_started_r;
522 calib_ref_done <= calib_start_shift0_r[15] |
523 calib_start_shift1_r[15] |
524 calib_start_shift3_r[15];
527 // generate delay for various states that require it (no maximum delay
528 // requirement, make sure that terminal count is large enough to cover
530 always @(posedge clkdiv0) begin
533 INIT_MODE_REGISTER_WAIT,
534 INIT_AUTO_REFRESH_WAIT,
535 INIT_DUMMY_ACTIVE_WAIT,
536 INIT_CAL1_WRITE_READ,
538 INIT_CAL2_WRITE_READ,
540 INIT_CAL3_WRITE_READ:
541 cnt_cmd_r <= cnt_cmd_r + 1;
543 cnt_cmd_r <= 7'b0000000;
547 // assert when count reaches the value
548 always @(posedge clkdiv0) begin
549 if(cnt_cmd_r == CNTNEXT_CMD)
550 cnt_cmd_ok_r <= 1'b1;
552 cnt_cmd_ok_r <= 1'b0;
555 always @(posedge clkdiv0) begin
559 cnt_rd_r <= cnt_rd_r + 1;
565 always @(posedge clkdiv0) begin
566 if(cnt_rd_r == CNTNEXT_RD)
572 //***************************************************************************
573 // Initial delay after power-on
574 //***************************************************************************
576 // register the refresh flag from the controller.
577 // The refresh flag is in full frequency domain - so a pulsed version must
578 // be generated for half freq domain using 2 consecutive full clk cycles
579 // The registered version is used for the 200us counter
580 always @(posedge clk0)
581 ctrl_ref_flag_r <= ctrl_ref_flag;
582 always @(posedge clkdiv0)
583 cke_200us_cnt_en_r <= ctrl_ref_flag || ctrl_ref_flag_r;
585 // 200us counter for cke
586 always @(posedge clkdiv0)
588 // skip power-up count if only simulating
590 cke_200us_cnt_r <= 5'b00001;
592 cke_200us_cnt_r <= 5'd27;
593 end else if (cke_200us_cnt_en_r)
594 cke_200us_cnt_r <= cke_200us_cnt_r - 1;
596 always @(posedge clkdiv0)
598 done_200us_r <= 1'b0;
599 else if (!done_200us_r)
600 done_200us_r <= (cke_200us_cnt_r == 5'b00000);
602 // 200 clocks counter - count value : h'64 required for initialization
603 // Counts 100 divided by two clocks
604 always @(posedge clkdiv0)
605 if (rstdiv0 || (init_state_r == INIT_CNT_200))
606 cnt_200_cycle_r <= 8'h64;
607 else if (init_state_r == INIT_ZQCL) // ddr3
608 cnt_200_cycle_r <= 8'hC8;
609 else if (cnt_200_cycle_r != 8'h00)
610 cnt_200_cycle_r <= cnt_200_cycle_r - 1;
612 always @(posedge clkdiv0)
613 if (rstdiv0 || (init_state_r == INIT_CNT_200)
614 || (init_state_r == INIT_ZQCL))
615 cnt_200_cycle_done_r <= 1'b0;
616 else if (cnt_200_cycle_r == 8'h00)
617 cnt_200_cycle_done_r <= 1'b1;
619 //*****************************************************************
620 // handle deep memory configuration:
621 // During initialization: Repeat initialization sequence once for each
622 // chip select. Note that we could perform initalization for all chip
623 // selects simulataneously. Probably fine - any potential SI issues with
624 // auto refreshing all chip selects at once?
625 // Once initialization complete, assert only CS[0] for calibration.
626 //*****************************************************************
628 always @(posedge clkdiv0)
631 end else if (init_state_r == INIT_DEEP_MEMORY_ST) begin
632 if (chip_cnt_r != CS_NUM)
633 chip_cnt_r <= chip_cnt_r + 1;
638 always @(posedge clkdiv0)
640 ddr_cs_n_r <= {CS_NUM{1'b1}};
642 ddr_cs_n_r <= {CS_NUM{1'b1}};
643 if ((init_state_r == INIT_DUMMY_ACTIVE) ||
644 (init_state_r == INIT_PRECHARGE) ||
645 (init_state_r == INIT_LOAD_MODE) ||
646 (init_state_r == INIT_AUTO_REFRESH) ||
647 (init_state_r == INIT_ZQCL ) ||
648 (((init_state_r == INIT_CAL1_READ) ||
649 (init_state_r == INIT_CAL2_READ) ||
650 (init_state_r == INIT_CAL3_READ) ||
651 (init_state_r == INIT_CAL4_READ) ||
652 (init_state_r == INIT_CAL1_WRITE) ||
653 (init_state_r == INIT_CAL2_WRITE) ||
654 (init_state_r == INIT_CAL3_WRITE)) && (burst_cnt_r == 2'b00)))
655 ddr_cs_n_r[chip_cnt_r] <= 1'b0;
657 ddr_cs_n_r[chip_cnt_r] <= 1'b1;
660 //***************************************************************************
661 // Write/read burst logic
662 //***************************************************************************
664 assign cal_write = ((init_state_r == INIT_CAL1_WRITE) ||
665 (init_state_r == INIT_CAL2_WRITE) ||
666 (init_state_r == INIT_CAL3_WRITE));
667 assign cal_read = ((init_state_r == INIT_CAL1_READ) ||
668 (init_state_r == INIT_CAL2_READ) ||
669 (init_state_r == INIT_CAL3_READ) ||
670 (init_state_r == INIT_CAL4_READ));
671 assign cal_write_read = ((init_state_r == INIT_CAL1_READ) ||
672 (init_state_r == INIT_CAL2_READ) ||
673 (init_state_r == INIT_CAL3_READ) ||
674 (init_state_r == INIT_CAL4_READ) ||
675 (init_state_r == INIT_CAL1_WRITE) ||
676 (init_state_r == INIT_CAL2_WRITE) ||
677 (init_state_r == INIT_CAL3_WRITE));
679 assign burst_val = (BURST_LEN == 4) ? 2'b00 :
680 (BURST_LEN == 8) ? 2'b01 : 2'b00;
682 // keep track of current address - need this if burst length < 8 for
683 // stage 2-4 calibration writes and reads. Make sure value always gets
684 // initialized to 0 before we enter write/read state. This is used to
685 // keep track of when another burst must be issued
686 always @(posedge clkdiv0)
688 burst_addr_r <= burst_addr_r + 2;
690 burst_addr_r <= 2'b00;
692 // write/read burst count
693 always @(posedge clkdiv0)
695 if (burst_cnt_r == 2'b00)
696 burst_cnt_r <= burst_val;
697 else // SHOULD THIS BE -2 CHECK THIS LOGIC
698 burst_cnt_r <= burst_cnt_r - 1;
700 burst_cnt_r <= 2'b00;
702 // indicate when a write is occurring
703 always @(posedge clkdiv0)
704 // MIG 2.1: Remove (burst_addr_r<4) term - not used
705 // phy_init_wren <= cal_write && (burst_addr_r < 3'd4);
706 phy_init_wren <= cal_write;
708 // used for read enable calibration, pulse to indicate when read issued
709 always @(posedge clkdiv0)
710 // MIG 2.1: Remove (burst_addr_r<4) term - not used
711 // phy_init_rden <= cal_read && (burst_addr_r < 3'd4);
712 phy_init_rden <= cal_read;
714 //***************************************************************************
715 // Initialization state machine
716 //***************************************************************************
718 always @(posedge clkdiv0)
719 // every time we need to initialize another rank of memory, need to
720 // reset init count, and repeat the entire initialization (but not
721 // calibration) sequence
722 if (rstdiv0 || (init_state_r == INIT_DEEP_MEMORY_ST))
723 init_cnt_r <= INIT_CNTR_INIT;
724 else if ((DDR_TYPE == DDR1) && (init_state_r == INIT_PRECHARGE) &&
725 (init_cnt_r == INIT_CNTR_PRECH_1))
726 // skip EMR(2) and EMR(3) register loads
727 init_cnt_r <= INIT_CNTR_EMR_EN_DLL;
728 else if ((DDR_TYPE == DDR1) && (init_state_r == INIT_LOAD_MODE) &&
729 (init_cnt_r == INIT_CNTR_MR_ACT_DLL))
730 // skip OCD calibration for DDR1
731 init_cnt_r <= INIT_CNTR_DEEP_MEM;
732 else if ((DDR_TYPE == DDR3) && (init_state_r == INIT_ZQCL))
733 // skip states for DDR3
734 init_cnt_r <= INIT_CNTR_DEEP_MEM;
735 else if ((init_state_r == INIT_LOAD_MODE) ||
736 ((init_state_r == INIT_PRECHARGE)
737 && (init_state_r1 != INIT_CALIB_REF))||
738 ((init_state_r == INIT_AUTO_REFRESH)
740 (init_state_r == INIT_CNT_200))
741 init_cnt_r <= init_cnt_r + 1;
743 always @(posedge clkdiv0) begin
744 if ((init_state_r == INIT_IDLE) && (init_cnt_r == INIT_CNTR_DONE)) begin
745 phy_init_done_r <= 1'b1;
747 phy_init_done_r <= 1'b0;
750 // phy_init_done to the controller and the user interface.
751 // It is delayed by four clocks to account for the
752 // multi cycle path constraint to the (phy_init_data_sel)
754 always @(posedge clkdiv0)begin
755 phy_init_done_r1 <= phy_init_done_r;
756 phy_init_done_r2 <= phy_init_done_r1;
757 phy_init_done_r3 <= phy_init_done_r2;
758 phy_init_done <= phy_init_done_r3;
761 // Instantiate primitive to allow this flop to be attached to multicycle
762 // path constraint in UCF. This signal goes to PHY_WRITE and PHY_CTL_IO
763 // datapath logic only. Because it is a multi-cycle path, it can be
764 // clocked by either CLKDIV0 or CLK0.
765 FDRSE u_ff_phy_init_data_sel
767 .Q (phy_init_data_sel),
770 .D (phy_init_done_r1),
776 //synthesis translate_off
777 always @(posedge calib_done[0])
778 $display ("First Stage Calibration completed at time %t", $time);
780 always @(posedge calib_done[1])
781 $display ("Second Stage Calibration completed at time %t", $time);
783 always @(posedge calib_done[2]) begin
784 $display ("Third Stage Calibration completed at time %t", $time);
787 always @(posedge calib_done[3]) begin
788 $display ("Fourth Stage Calibration completed at time %t", $time);
789 $display ("Calibration completed at time %t", $time);
791 //synthesis translate_on
793 always @(posedge clkdiv0) begin
794 if ((init_cnt_r >= INIT_CNTR_DEEP_MEM))begin
800 //*****************************************************************
802 always @(posedge clkdiv0)
804 init_state_r <= INIT_IDLE;
805 init_state_r1 <= INIT_IDLE;
806 init_state_r2 <= INIT_IDLE;
807 calib_done_r <= 4'b0000;
809 init_state_r <= init_next_state;
810 init_state_r1 <= init_state_r;
811 init_state_r2 <= init_state_r1;
812 calib_done_r <= calib_done; // register for timing
816 init_next_state = init_state_r;
817 (* full_case, parallel_case *) case (init_state_r)
819 if (done_200us_r) begin
820 (* parallel_case *) case (init_cnt_r)
822 init_next_state = INIT_CNT_200;
824 init_next_state = INIT_PRECHARGE;
826 init_next_state = INIT_LOAD_MODE; // EMR(2)
828 init_next_state = INIT_LOAD_MODE; // EMR(3);
829 INIT_CNTR_EMR_EN_DLL:
830 init_next_state = INIT_LOAD_MODE; // EMR, enable DLL
831 INIT_CNTR_MR_RST_DLL:
832 init_next_state = INIT_LOAD_MODE; // MR, reset DLL
833 INIT_CNTR_CNT_200_WAIT:begin
835 init_next_state = INIT_ZQCL; // DDR3
837 // Wait 200cc after reset DLL
838 init_next_state = INIT_CNT_200;
841 init_next_state = INIT_PRECHARGE;
843 init_next_state = INIT_AUTO_REFRESH;
845 init_next_state = INIT_AUTO_REFRESH;
846 INIT_CNTR_MR_ACT_DLL:
847 init_next_state = INIT_LOAD_MODE; // MR, unreset DLL
848 INIT_CNTR_EMR_DEF_OCD:
849 init_next_state = INIT_LOAD_MODE; // EMR, OCD default
850 INIT_CNTR_EMR_EXIT_OCD:
851 init_next_state = INIT_LOAD_MODE; // EMR, enable OCD exit
852 INIT_CNTR_DEEP_MEM: begin
853 if ((chip_cnt_r < CS_NUM-1))
854 init_next_state = INIT_DEEP_MEMORY_ST;
855 else if (cnt_200_cycle_done_r)
856 init_next_state = INIT_DUMMY_ACTIVE;
858 init_next_state = INIT_IDLE;
861 init_next_state = INIT_PRECHARGE;
863 init_next_state = INIT_IDLE;
865 init_next_state = INIT_IDLE;
870 init_next_state = INIT_CNT_200_WAIT;
872 if (cnt_200_cycle_done_r)
873 init_next_state = INIT_IDLE;
875 init_next_state = INIT_PRECHARGE_WAIT;
877 if (cnt_cmd_ok_r)begin
878 if (init_done_r && (!(&calib_done_r)))
879 init_next_state = INIT_AUTO_REFRESH;
881 init_next_state = INIT_IDLE;
884 init_next_state = INIT_WAIT_DLLK_ZQINIT;
885 INIT_WAIT_DLLK_ZQINIT:
886 if (cnt_200_cycle_done_r)
887 init_next_state = INIT_IDLE;
889 init_next_state = INIT_MODE_REGISTER_WAIT;
890 INIT_MODE_REGISTER_WAIT:
892 init_next_state = INIT_IDLE;
894 init_next_state = INIT_AUTO_REFRESH_WAIT;
895 INIT_AUTO_REFRESH_WAIT:
896 if (cnt_cmd_ok_r)begin
898 init_next_state = INIT_DUMMY_ACTIVE;
900 init_next_state = INIT_IDLE;
903 init_next_state = INIT_IDLE;
904 // single row activate. All subsequent calibration writes and
905 // read will take place in this row
907 init_next_state = INIT_DUMMY_ACTIVE_WAIT;
908 INIT_DUMMY_ACTIVE_WAIT:
909 if (cnt_cmd_ok_r)begin
910 if (~calib_done_r[0]) begin
911 // if returning to stg1 after refresh, don't need to write
913 init_next_state = INIT_CAL1_READ;
914 // if first entering stg1, need to write training pattern
916 init_next_state = INIT_CAL1_WRITE;
917 end else if (~calib_done[1]) begin
919 init_next_state = INIT_CAL2_READ;
921 init_next_state = INIT_CAL2_WRITE;
922 end else if (~calib_done_r[2])
923 init_next_state = INIT_CAL3_WRITE;
925 init_next_state = INIT_CAL4_READ;
927 // Stage 1 calibration (write and continuous read)
929 if (burst_addr_r == 2'b10)
930 init_next_state = INIT_CAL1_WRITE_READ;
931 INIT_CAL1_WRITE_READ:
933 init_next_state = INIT_CAL1_READ;
935 // Stage 1 requires inter-stage auto-refresh
936 if (calib_done_r[0] || refresh_req)
937 init_next_state = INIT_CAL1_READ_WAIT;
940 init_next_state = INIT_CALIB_REF;
941 // Stage 2 calibration (write and continuous read)
943 if (burst_addr_r == 2'b10)
944 init_next_state = INIT_CAL2_WRITE_READ;
945 INIT_CAL2_WRITE_READ:
947 init_next_state = INIT_CAL2_READ;
949 // Stage 2 requires inter-stage auto-refresh
950 if (calib_done_r[1] || refresh_req)
951 init_next_state = INIT_CAL2_READ_WAIT;
954 init_next_state = INIT_CALIB_REF;
955 // Stage 3 calibration (write and continuous read)
957 if (burst_addr_r == 2'b10)
958 init_next_state = INIT_CAL3_WRITE_READ;
959 INIT_CAL3_WRITE_READ:
961 init_next_state = INIT_CAL3_READ;
963 if (burst_addr_r == 2'b10)
964 init_next_state = INIT_CAL3_READ_WAIT;
965 INIT_CAL3_READ_WAIT: begin
967 if (calib_done_r[2]) begin
968 init_next_state = INIT_CALIB_REF;
970 init_next_state = INIT_CAL3_READ;
972 // Stage 4 calibration (continuous read only, same pattern as stage 3)
973 // only used if DQS_GATE supported
975 if (burst_addr_r == 2'b10)
976 init_next_state = INIT_CAL4_READ_WAIT;
977 INIT_CAL4_READ_WAIT: begin
979 // Stage 4 requires inter-stage auto-refresh
980 if (calib_done_r[3] || refresh_req)
981 init_next_state = INIT_PRECHARGE;
983 init_next_state = INIT_CAL4_READ;
986 init_next_state = INIT_PRECHARGE;
990 //***************************************************************************
991 // Memory control/address
992 //***************************************************************************
994 always @(posedge clkdiv0)
995 if ((init_state_r == INIT_DUMMY_ACTIVE) ||
996 (init_state_r == INIT_PRECHARGE) ||
997 (init_state_r == INIT_LOAD_MODE) ||
998 (init_state_r == INIT_AUTO_REFRESH)) begin
1001 ddr_ras_n_r <= 1'b1;
1004 always @(posedge clkdiv0)
1005 if ((init_state_r == INIT_LOAD_MODE) ||
1006 (init_state_r == INIT_AUTO_REFRESH) ||
1007 (cal_write_read && (burst_cnt_r == 2'b00))) begin
1008 ddr_cas_n_r <= 1'b0;
1010 ddr_cas_n_r <= 1'b1;
1013 always @(posedge clkdiv0)
1014 if ((init_state_r == INIT_LOAD_MODE) ||
1015 (init_state_r == INIT_PRECHARGE) ||
1016 (init_state_r == INIT_ZQCL) ||
1017 (cal_write && (burst_cnt_r == 2'b00)))begin
1023 //*****************************************************************
1024 // memory address during init
1025 //*****************************************************************
1027 always @(posedge clkdiv0) begin
1028 if ((init_state_r == INIT_PRECHARGE)
1029 || (init_state_r == INIT_ZQCL))begin
1030 // Precharge all - set A10 = 1
1031 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1032 ddr_addr_r[10] <= 1'b1;
1033 ddr_ba_r <= {BANK_WIDTH{1'b0}};
1034 end else if (init_state_r == INIT_LOAD_MODE) begin
1035 ddr_ba_r <= {BANK_WIDTH{1'b0}};
1036 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1039 INIT_CNTR_EMR2_INIT: begin
1040 ddr_ba_r[1:0] <= 2'b10;
1041 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1044 INIT_CNTR_EMR3_INIT: begin
1045 ddr_ba_r[1:0] <= 2'b11;
1046 if(DDR_TYPE == DDR3)
1047 ddr_addr_r <= load_mode_reg3[ROW_WIDTH-1:0];
1049 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1051 // EMR write - A0 = 0 for DLL enable
1052 INIT_CNTR_EMR_EN_DLL: begin
1053 ddr_ba_r[1:0] <= 2'b01;
1054 if(DDR_TYPE == DDR3)
1055 ddr_addr_r <= load_mode_reg1[ROW_WIDTH-1:0];
1057 ddr_addr_r <= ext_mode_reg[ROW_WIDTH-1:0];
1059 // MR write, reset DLL (A8=1)
1060 INIT_CNTR_MR_RST_DLL: begin
1061 if(DDR_TYPE == DDR3)
1062 ddr_addr_r <= load_mode_reg0[ROW_WIDTH-1:0];
1064 ddr_addr_r <= load_mode_reg[ROW_WIDTH-1:0];
1065 ddr_ba_r[1:0] <= 2'b00;
1066 ddr_addr_r[8] <= 1'b1;
1068 // MR write, unreset DLL (A8=0)
1069 INIT_CNTR_MR_ACT_DLL: begin
1070 ddr_ba_r[1:0] <= 2'b00;
1071 ddr_addr_r <= load_mode_reg[ROW_WIDTH-1:0];
1073 // EMR write, OCD default state
1074 INIT_CNTR_EMR_DEF_OCD: begin
1075 ddr_ba_r[1:0] <= 2'b01;
1076 ddr_addr_r <= ext_mode_reg[ROW_WIDTH-1:0];
1077 ddr_addr_r[9:7] <= 3'b111;
1079 // EMR write - OCD exit
1080 INIT_CNTR_EMR_EXIT_OCD: begin
1081 ddr_ba_r[1:0] <= 2'b01;
1082 ddr_addr_r <= ext_mode_reg[ROW_WIDTH-1:0];
1085 ddr_ba_r <= {BANK_WIDTH{1'bx}};
1086 ddr_addr_r <= {ROW_WIDTH{1'bx}};
1089 end else if (cal_write_read) begin
1090 // when writing or reading for Stages 2-4, since training pattern is
1091 // either 4 (stage 2) or 8 (stage 3-4) long, if BURST LEN < 8, then
1092 // need to issue multiple bursts to read entire training pattern
1093 ddr_addr_r[ROW_WIDTH-1:3] <= {ROW_WIDTH-4{1'b0}};
1094 ddr_addr_r[2:0] <= {burst_addr_r, 1'b0};
1095 ddr_ba_r <= {BANK_WIDTH-1{1'b0}};
1096 end else if (init_state_r == INIT_DUMMY_ACTIVE) begin
1097 // all calibration writing read takes place in row 0x0 only
1098 ddr_ba_r <= {BANK_WIDTH{1'b0}};
1099 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1101 // otherwise, cry me a river
1102 ddr_ba_r <= {BANK_WIDTH{1'bx}};
1103 ddr_addr_r <= {ROW_WIDTH{1'bx}};
1107 // Keep CKE asserted after initial power-on delay
1108 always @(posedge clkdiv0)
1109 ddr_cke_r <= {CKE_WIDTH{done_200us_r}};
1111 // register commands to memory. Two clock cycle delay from state -> output
1112 always @(posedge clk0) begin
1113 ddr_addr_r1 <= ddr_addr_r;
1114 ddr_ba_r1 <= ddr_ba_r;
1115 ddr_cas_n_r1 <= ddr_cas_n_r;
1116 ddr_ras_n_r1 <= ddr_ras_n_r;
1117 ddr_we_n_r1 <= ddr_we_n_r;
1118 ddr_cs_n_r1 <= ddr_cs_n_r;
1119 end // always @ (posedge clk0)
1121 // logic to toggle chip select. The chip_select is
1122 // clocked of clkdiv0 and will be asserted for
1123 // two clock cycles.
1124 always @(posedge clk0) begin
1126 ddr_cs_disable_r <= {CS_NUM{1'b0}};
1128 if(ddr_cs_disable_r[chip_cnt_r])
1129 ddr_cs_disable_r[chip_cnt_r] <= 1'b0;
1132 ddr_cs_disable_r[chip_cnt_r] <= ~ddr_cs_n_r1[chip_cnt_r];
1134 ddr_cs_disable_r[chip_cnt_r] <= ~ddr_cs_n_r[chip_cnt_r];
1140 assign phy_init_addr = ddr_addr_r;
1141 assign phy_init_ba = ddr_ba_r;
1142 assign phy_init_cas_n = ddr_cas_n_r;
1143 assign phy_init_cke = ddr_cke_r;
1144 assign phy_init_ras_n = ddr_ras_n_r;
1145 assign phy_init_we_n = ddr_we_n_r;
1146 assign phy_init_cs_n = (TWO_T_TIME_EN) ?
1147 ddr_cs_n_r1 | ddr_cs_disable_r
1148 : ddr_cs_n_r| ddr_cs_disable_r;