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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_usr_top.v
50 // /___/ /\ Date Last Modified: $Date: 2008/05/08 15:20:47 $
51 // \ \ / \ Date Created: Mon Aug 28 2006
57 // This module interfaces with the user. The user should provide the data
58 // and various commands.
61 //*****************************************************************************
67 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
68 // board design). Actual values may be different. Actual parameters values
69 // are passed from design top module ddr2_sdram module. Please refer to
70 // the ddr2_sdram module for actual values.
71 parameter BANK_WIDTH = 2,
72 parameter CS_BITS = 0,
73 parameter COL_WIDTH = 10,
74 parameter DQ_WIDTH = 72,
75 parameter DQ_PER_DQS = 8,
76 parameter APPDATA_WIDTH = 144,
77 parameter ECC_ENABLE = 0,
78 parameter DQS_WIDTH = 9,
79 parameter ROW_WIDTH = 14
85 input [DQ_WIDTH-1:0] rd_data_in_rise,
86 input [DQ_WIDTH-1:0] rd_data_in_fall,
87 input [DQS_WIDTH-1:0] phy_calib_rden,
88 input [DQS_WIDTH-1:0] phy_calib_rden_sel,
90 output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
91 input [2:0] app_af_cmd,
92 input [30:0] app_af_addr,
96 output [30:0] af_addr,
99 output [1:0] rd_ecc_error,
101 input [APPDATA_WIDTH-1:0] app_wdf_data,
102 input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
104 output app_wdf_afull,
105 output [(2*DQ_WIDTH)-1:0] wdf_data,
106 output [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data
109 wire [(APPDATA_WIDTH/2)-1:0] i_rd_data_fifo_out_fall;
110 wire [(APPDATA_WIDTH/2)-1:0] i_rd_data_fifo_out_rise;
112 //***************************************************************************
114 assign rd_data_fifo_out = {i_rd_data_fifo_out_fall,
115 i_rd_data_fifo_out_rise};
117 // read data de-skew and ECC calculation
120 .DQ_PER_DQS (DQ_PER_DQS),
121 .ECC_ENABLE (ECC_ENABLE),
122 .APPDATA_WIDTH (APPDATA_WIDTH),
123 .DQS_WIDTH (DQS_WIDTH)
129 .rd_data_in_rise (rd_data_in_rise),
130 .rd_data_in_fall (rd_data_in_fall),
131 .rd_ecc_error (rd_ecc_error),
132 .ctrl_rden (phy_calib_rden),
133 .ctrl_rden_sel (phy_calib_rden_sel),
134 .rd_data_valid (rd_data_valid),
135 .rd_data_out_rise (i_rd_data_fifo_out_rise),
136 .rd_data_out_fall (i_rd_data_fifo_out_fall)
139 // Command/Addres FIFO
142 .BANK_WIDTH (BANK_WIDTH),
143 .COL_WIDTH (COL_WIDTH),
145 .ROW_WIDTH (ROW_WIDTH)
151 .app_af_cmd (app_af_cmd),
152 .app_af_addr (app_af_addr),
153 .app_af_wren (app_af_wren),
154 .ctrl_af_rden (ctrl_af_rden),
157 .af_empty (af_empty),
158 .app_af_afull (app_af_afull)
163 .BANK_WIDTH (BANK_WIDTH),
164 .COL_WIDTH (COL_WIDTH),
166 .DQ_WIDTH (DQ_WIDTH),
167 .APPDATA_WIDTH (APPDATA_WIDTH),
168 .ECC_ENABLE (ECC_ENABLE),
169 .ROW_WIDTH (ROW_WIDTH)
176 .app_wdf_wren (app_wdf_wren),
177 .app_wdf_data (app_wdf_data),
178 .app_wdf_mask_data (app_wdf_mask_data),
179 .wdf_rden (wdf_rden),
180 .app_wdf_afull (app_wdf_afull),
181 .wdf_data (wdf_data),
182 .wdf_mask_data (wdf_mask_data)