src/edu/berkeley/fleet/fpga/greg/asyncfifo_dmem_1b.v

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  29 // The synthesis directives "translate_off/translate_on" specified below are
  30 // supported by Xilinx, Mentor Graphics and Synplicity synthesis
  31 // tools. Ensure they are correct for your synthesis tool(s).
  32
  33 // You must compile the wrapper file asyncfifo_dmem_1b.v when simulating
  34 // the core, asyncfifo_dmem_1b. When compiling the wrapper file, be sure to
  35 // reference the XilinxCoreLib Verilog simulation library. For detailed
  36 // instructions, please refer to the "CORE Generator Help".
  37
  38 `timescale 1ns/1ps
  39
  40 module asyncfifo_dmem_1b(
  41         din,
  42         rd_clk,
  43         rd_en,
  44         rst,
  45         wr_clk,
  46         wr_en,
  47         dout,
  48         empty,
  49         full);
  50
  51
  52 input [0 : 0] din;
  53 input rd_clk;
  54 input rd_en;
  55 input rst;
  56 input wr_clk;
  57 input wr_en;
  58 output [0 : 0] dout;
  59 output empty;
  60 output full;
  61
  62 // synthesis translate_off
  63
  64       FIFO_GENERATOR_V4_3 #(
  65                 .C_COMMON_CLOCK(0),
  66                 .C_COUNT_TYPE(0),
  67                 .C_DATA_COUNT_WIDTH(6),
  68                 .C_DEFAULT_VALUE("BlankString"),
  69                 .C_DIN_WIDTH(1),
  70                 .C_DOUT_RST_VAL("0"),
  71                 .C_DOUT_WIDTH(1),
  72                 .C_ENABLE_RLOCS(0),
  73                 .C_FAMILY("virtex5"),
  74                 .C_FULL_FLAGS_RST_VAL(1),
  75                 .C_HAS_ALMOST_EMPTY(0),
  76                 .C_HAS_ALMOST_FULL(0),
  77                 .C_HAS_BACKUP(0),
  78                 .C_HAS_DATA_COUNT(0),
  79                 .C_HAS_INT_CLK(0),
  80                 .C_HAS_MEMINIT_FILE(0),
  81                 .C_HAS_OVERFLOW(0),
  82                 .C_HAS_RD_DATA_COUNT(0),
  83                 .C_HAS_RD_RST(0),
  84                 .C_HAS_RST(1),
  85                 .C_HAS_SRST(0),
  86                 .C_HAS_UNDERFLOW(0),
  87                 .C_HAS_VALID(0),
  88                 .C_HAS_WR_ACK(0),
  89                 .C_HAS_WR_DATA_COUNT(0),
  90                 .C_HAS_WR_RST(0),
  91                 .C_IMPLEMENTATION_TYPE(2),
  92                 .C_INIT_WR_PNTR_VAL(0),
  93                 .C_MEMORY_TYPE(2),
  94                 .C_MIF_FILE_NAME("BlankString"),
  95                 .C_MSGON_VAL(1),
  96                 .C_OPTIMIZATION_MODE(0),
  97                 .C_OVERFLOW_LOW(0),
  98                 .C_PRELOAD_LATENCY(0),
  99                 .C_PRELOAD_REGS(1),
 100                 .C_PRIM_FIFO_TYPE("512x36"),
 101                 .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
 102                 .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
 103                 .C_PROG_EMPTY_TYPE(0),
 104                 .C_PROG_FULL_THRESH_ASSERT_VAL(62),
 105                 .C_PROG_FULL_THRESH_NEGATE_VAL(61),
 106                 .C_PROG_FULL_TYPE(0),
 107                 .C_RD_DATA_COUNT_WIDTH(6),
 108                 .C_RD_DEPTH(64),
 109                 .C_RD_FREQ(1),
 110                 .C_RD_PNTR_WIDTH(6),
 111                 .C_UNDERFLOW_LOW(0),
 112                 .C_USE_DOUT_RST(1),
 113                 .C_USE_ECC(0),
 114                 .C_USE_EMBEDDED_REG(0),
 115                 .C_USE_FIFO16_FLAGS(0),
 116                 .C_USE_FWFT_DATA_COUNT(0),
 117                 .C_VALID_LOW(0),
 118                 .C_WR_ACK_LOW(0),
 119                 .C_WR_DATA_COUNT_WIDTH(6),
 120                 .C_WR_DEPTH(64),
 121                 .C_WR_FREQ(1),
 122                 .C_WR_PNTR_WIDTH(6),
 123                 .C_WR_RESPONSE_LATENCY(1))
 124         inst (
 125                 .DIN(din),
 126                 .RD_CLK(rd_clk),
 127                 .RD_EN(rd_en),
 128                 .RST(rst),
 129                 .WR_CLK(wr_clk),
 130                 .WR_EN(wr_en),
 131                 .DOUT(dout),
 132                 .EMPTY(empty),
 133                 .FULL(full),
 134                 .CLK(),
 135                 .INT_CLK(),
 136                 .BACKUP(),
 137                 .BACKUP_MARKER(),
 138                 .PROG_EMPTY_THRESH(),
 139                 .PROG_EMPTY_THRESH_ASSERT(),
 140                 .PROG_EMPTY_THRESH_NEGATE(),
 141                 .PROG_FULL_THRESH(),
 142                 .PROG_FULL_THRESH_ASSERT(),
 143                 .PROG_FULL_THRESH_NEGATE(),
 144                 .RD_RST(),
 145                 .SRST(),
 146                 .WR_RST(),
 147                 .ALMOST_EMPTY(),
 148                 .ALMOST_FULL(),
 149                 .DATA_COUNT(),
 150                 .OVERFLOW(),
 151                 .PROG_EMPTY(),
 152                 .PROG_FULL(),
 153                 .VALID(),
 154                 .RD_DATA_COUNT(),
 155                 .UNDERFLOW(),
 156                 .WR_ACK(),
 157                 .WR_DATA_COUNT(),
 158                 .SBITERR(),
 159                 .DBITERR());
 160
 161
 162 // synthesis translate_on
 163
 164 endmodule
 165