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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_ctrl.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/29 15:24:03 $
51 // \ \ / \ Date Created: Wed Aug 30 2006
56 //Design Name: DDR/DDR2
58 // This module is the main control logic of the memory interface. All
59 // commands are issued from here according to the burst, CAS Latency and the
63 // Rev 1.2 - Fixed auto refresh to activate bug. KP 11-19-2007
64 // Rev 1.3 - For Dual Rank parts support CS logic modified. KP. 05/08/08
65 // Rev 1.4 - AUTO_REFRESH_WAIT state modified for Auto Refresh flag asserted
66 // immediately after calibration is completed. KP. 07/28/08
67 //*****************************************************************************
73 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
74 // board design). Actual values may be different. Actual parameters values
75 // are passed from design top module ddr2_sdram module. Please refer to
76 // the ddr2_sdram module for actual values.
77 parameter BANK_WIDTH = 2,
78 parameter COL_WIDTH = 10,
79 parameter CS_BITS = 0,
81 parameter ROW_WIDTH = 14,
82 parameter ADDITIVE_LAT = 0,
83 parameter BURST_LEN = 4,
84 parameter CAS_LAT = 5,
85 parameter ECC_ENABLE = 0,
86 parameter REG_ENABLE = 1,
87 parameter TREFI_NS = 7800,
88 parameter TRAS = 40000,
89 parameter TRCD = 15000,
90 parameter TRRD = 10000,
91 parameter TRFC = 105000,
92 parameter TRP = 15000,
93 parameter TRTP = 7500,
94 parameter TWR = 15000,
95 parameter TWTR = 10000,
96 parameter CLK_PERIOD = 3000,
97 parameter MULTI_BANK_EN = 1,
98 parameter TWO_T_TIME_EN = 0,
99 parameter DDR_TYPE = 1
105 input [30:0] af_addr,
109 output reg wr_fifo_burst,
111 output ctrl_ref_flag,
113 output reg ctrl_wren,
114 output reg ctrl_rden,
115 output [ROW_WIDTH-1:0] ctrl_addr,
116 output [BANK_WIDTH-1:0] ctrl_ba,
120 output [CS_NUM-1:0] ctrl_cs_n
123 // input address split into various ranges
124 localparam ROW_RANGE_START = COL_WIDTH;
125 localparam ROW_RANGE_END = ROW_WIDTH + ROW_RANGE_START - 1;
126 localparam BANK_RANGE_START = ROW_RANGE_END + 1;
127 localparam BANK_RANGE_END = BANK_WIDTH + BANK_RANGE_START - 1;
128 localparam CS_RANGE_START = BANK_RANGE_START + BANK_WIDTH;
129 localparam CS_RANGE_END = CS_BITS + CS_RANGE_START - 1;
130 // compare address (for determining bank/row hits) split into various ranges
131 // (compare address doesn't include column bits)
132 localparam CMP_WIDTH = CS_BITS + BANK_WIDTH + ROW_WIDTH;
133 localparam CMP_ROW_RANGE_START = 0;
134 localparam CMP_ROW_RANGE_END = ROW_WIDTH + CMP_ROW_RANGE_START - 1;
135 localparam CMP_BANK_RANGE_START = CMP_ROW_RANGE_END + 1;
136 localparam CMP_BANK_RANGE_END = BANK_WIDTH + CMP_BANK_RANGE_START - 1;
137 localparam CMP_CS_RANGE_START = CMP_BANK_RANGE_END + 1;
138 localparam CMP_CS_RANGE_END = CS_BITS + CMP_CS_RANGE_START-1;
140 localparam BURST_LEN_DIV2 = BURST_LEN / 2;
141 localparam OPEN_BANK_NUM = 4;
142 localparam CS_BITS_FIX = (CS_BITS == 0) ? 1 : CS_BITS;
144 // calculation counters based on clock cycle and memory parameters
145 // TRAS: ACTIVE->PRECHARGE interval - 2
146 localparam integer TRAS_CYC = (TRAS + CLK_PERIOD)/CLK_PERIOD;
147 // TRCD: ACTIVE->READ/WRITE interval - 3 (for DDR2 factor in ADD_LAT)
148 localparam integer TRRD_CYC = (TRRD + CLK_PERIOD)/CLK_PERIOD;
149 localparam integer TRCD_CYC = (((TRCD + CLK_PERIOD)/CLK_PERIOD) >
151 ((TRCD+CLK_PERIOD)/ CLK_PERIOD) - ADDITIVE_LAT : 0;
152 // TRFC: REFRESH->REFRESH, REFRESH->ACTIVE interval - 2
153 localparam integer TRFC_CYC = (TRFC + CLK_PERIOD)/CLK_PERIOD;
154 // TRP: PRECHARGE->COMMAND interval - 2
155 // for precharge all add 1 extra clock cycle
156 localparam integer TRP_CYC = ((TRP + CLK_PERIOD)/CLK_PERIOD) +1;
157 // TRTP: READ->PRECHARGE interval - 2 (Al + BL/2 + (max (TRTP, 2tck))-2
158 localparam integer TRTP_TMP_MIN = (((TRTP + CLK_PERIOD)/CLK_PERIOD) >= 2)?
159 ((TRTP + CLK_PERIOD)/CLK_PERIOD) : 2;
160 localparam integer TRTP_CYC = TRTP_TMP_MIN + ADDITIVE_LAT
161 + BURST_LEN_DIV2 - 2;
162 // TWR: WRITE->PRECHARGE interval - 2
163 localparam integer WR_LAT = (DDR_TYPE > 0) ? CAS_LAT + ADDITIVE_LAT - 1 : 1;
164 localparam integer TWR_CYC = ((TWR + CLK_PERIOD)/CLK_PERIOD) +
165 WR_LAT + BURST_LEN_DIV2 ;
166 // TWTR: WRITE->READ interval - 3 (for DDR1, TWTR = 2 clks)
167 // DDR2 = CL-1 + BL/2 +TWTR
168 localparam integer TWTR_TMP_MIN = (TWTR + CLK_PERIOD)/CLK_PERIOD;
169 localparam integer TWTR_CYC = (DDR_TYPE > 0) ? (TWTR_TMP_MIN + (CAS_LAT -1)
170 + BURST_LEN_DIV2 ): 2;
172 // TRTW: READ->WRITE interval - 3
174 // DDR2: (BL/2) + 2. Two more clocks are added to
175 // the DDR2 counter to account for the delay in
176 // arrival of the DQS during reads (pcb trace + buffer
177 // delays + memory parameters).
178 localparam TRTW_CYC = (DDR_TYPE > 0) ? BURST_LEN_DIV2 + 4 :
179 (CAS_LAT == 25) ? 2 + BURST_LEN_DIV2 : CAS_LAT + BURST_LEN_DIV2;
181 localparam integer CAS_LAT_RD = (CAS_LAT == 25) ? 2 : CAS_LAT;
183 // Make sure all values >= 0 (some may be = 0)
184 localparam TRAS_COUNT = (TRAS_CYC > 0) ? TRAS_CYC : 0;
185 localparam TRCD_COUNT = (TRCD_CYC > 0) ? TRCD_CYC : 0;
186 localparam TRRD_COUNT = (TRRD_CYC > 0) ? TRRD_CYC : 0;
187 localparam TRFC_COUNT = (TRFC_CYC > 0) ? TRFC_CYC : 0;
188 localparam TRP_COUNT = (TRP_CYC > 0) ? TRP_CYC : 0;
189 localparam TRTP_COUNT = (TRTP_CYC > 0) ? TRTP_CYC : 0;
190 localparam TWR_COUNT = (TWR_CYC > 0) ? TWR_CYC : 0;
191 localparam TWTR_COUNT = (TWTR_CYC > 0) ? TWTR_CYC : 0;
192 localparam TRTW_COUNT = (TRTW_CYC > 0) ? TRTW_CYC : 0;
194 // Auto refresh interval
195 localparam TREFI_COUNT = ((TREFI_NS * 1000)/CLK_PERIOD) - 1;
197 // memory controller states
198 localparam CTRL_IDLE = 5'h00;
199 localparam CTRL_PRECHARGE = 5'h01;
200 localparam CTRL_PRECHARGE_WAIT = 5'h02;
201 localparam CTRL_AUTO_REFRESH = 5'h03;
202 localparam CTRL_AUTO_REFRESH_WAIT = 5'h04;
203 localparam CTRL_ACTIVE = 5'h05;
204 localparam CTRL_ACTIVE_WAIT = 5'h06;
205 localparam CTRL_BURST_READ = 5'h07;
206 localparam CTRL_READ_WAIT = 5'h08;
207 localparam CTRL_BURST_WRITE = 5'h09;
208 localparam CTRL_WRITE_WAIT = 5'h0A;
209 localparam CTRL_PRECHARGE_WAIT1 = 5'h0B;
212 reg [CMP_WIDTH-1:0] act_addr_r;
213 wire [30:0] af_addr_r;
214 reg [30:0] af_addr_r1;
215 reg [30:0] af_addr_r2;
216 reg [30:0] af_addr_r3;
223 reg [CS_BITS_FIX :0] auto_cnt_r;
225 reg [(OPEN_BANK_NUM*CMP_WIDTH)-1:0] bank_cmp_addr_r;
226 reg [OPEN_BANK_NUM-1:0] bank_hit;
227 reg [OPEN_BANK_NUM-1:0] bank_hit_r;
228 reg [OPEN_BANK_NUM-1:0] bank_hit_r1;
229 reg [OPEN_BANK_NUM-1:0] bank_valid_r;
231 reg conflict_resolved_r;
233 reg conflict_detect_r;
234 wire conflict_detect;
236 reg cs_change_sticky_r;
237 reg [ROW_WIDTH-1:0] ddr_addr_r;
238 wire [ROW_WIDTH-1:0] ddr_addr_col;
239 wire [ROW_WIDTH-1:0] ddr_addr_row;
240 reg [BANK_WIDTH-1:0] ddr_ba_r;
242 reg [CS_NUM-1:0] ddr_cs_n_r;
245 reg [4:0] next_state;
246 reg no_precharge_wait_r;
250 reg [4:0] precharge_ok_cnt_r;
255 reg [2:0] rdburst_cnt_r;
257 reg rdburst_rden_ok_r;
261 reg [4:0] rd_to_wr_cnt_r;
264 reg [11:0] refi_cnt_r;
267 /* synthesis syn_preserve = 1 */;
269 /* synthesis syn_maxfan = 10 */;
273 reg [3:0] row_conflict_r;
276 reg [CMP_WIDTH-1:0] sb_open_add_r;
281 reg [2:0] trrd_cnt_r;
283 reg [2:0] two_t_enable_r;
284 reg [CS_NUM-1:0] two_t_enable_r1;
285 reg [2:0] wrburst_cnt_r;
287 reg wrburst_wren_ok_r;
290 reg [4:0] wr_to_rd_cnt_r;
293 // XST attributes for local reset "tree"
294 // synthesis attribute shreg_extract of rst_r is "no";
295 // synthesis attribute shreg_extract of rst_r1 is "no";
296 // synthesis attribute equivalent_register_removal of rst_r is "no"
298 //***************************************************************************
300 // sm_rden is used to assert read enable to the address FIFO
301 assign sm_rden = ((state_r == CTRL_BURST_WRITE) ||
302 (state_r == CTRL_BURST_READ)) ;
304 // assert read flag to the adress FIFO
305 assign ctrl_af_rden = sm_rden || rd_af_flag_r;
307 // local reset "tree" for controller logic only. Create this to ease timing
308 // on reset path. Prohibit equivalent register removal on RST_R to prevent
309 // "sharing" with other local reset trees (caution: make sure global fanout
310 // limit is set to large enough value, otherwise SLICES may be used for
311 // fanout control on RST_R.
312 always @(posedge clk) begin
317 //*****************************************************************
318 // interpret commands from Command/Address FIFO
319 //*****************************************************************
321 assign wr_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b000) ? 1'b1 : 1'b0): 1'b0;
322 assign rd_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b001) ? 1'b1 : 1'b0): 1'b0;
324 always @(posedge clk) begin
325 rd_flag_r <= rd_flag;
326 wr_flag_r <= wr_flag;
329 //////////////////////////////////////////////////
330 // The data from the address FIFO is fetched and
331 // stored in two register stages. The data will be
332 // pulled out of the second register stage whenever
333 // the state machine can handle new data from the
336 // This flag is asserted when there is no
337 // cmd & address in the pipe. When there is
338 // valid cmd & addr from the address FIFO the
339 // af_valid signals will be asserted. This flag will
340 // be set the cycle af_valid_r is de-asserted.
341 always @(posedge clk) begin
342 // for simulation purposes - to force CTRL_AF_RDEN low during reset
344 rd_af_flag_r <= 1'd0;
345 else if((ctrl_af_rden_r) ||
346 (rd_af_flag_r && (af_valid_r || af_valid_r1)))
347 rd_af_flag_r <= 1'd0;
348 else if (~af_valid_r1 || ~af_valid_r)
349 rd_af_flag_r <= 1'd1;
353 // First register stage for the cmd & add from the FIFO.
354 // The af_valid_r signal gives the status of the data
355 // in this stage. The af_valid_r will be asserted when there
356 // is valid data. This register stage will be updated
357 // 1. read to the FIFO and the FIFO not empty
358 // 2. After write and read states
359 // 3. The valid signal is not asserted in the last stage.
360 always @(posedge clk) begin
364 if (ctrl_af_rden_r || sm_rden_r || ~af_valid_r1
365 || ~af_valid_r2)begin
366 af_valid_r <= ctrl_af_rden_r;
371 // The output register in the FIFO is used. The addr
372 // and command are already registered in the FIFO.
373 assign af_addr_r = af_addr;
374 assign af_cmd_r = af_cmd;
376 // Second register stage for the cmd & add from the FIFO.
377 // The af_valid_r1 signal gives the status of the data
378 // in this stage. The af_valid_r will be asserted when there
379 // is valid data. This register stage will be updated
380 // 1. read to the FIFO and the FIFO not empty and there
381 // is no valid data on this stage
382 // 2. After write and read states
383 // 3. The valid signal is not asserted in the last stage.
384 always@(posedge clk) begin
387 af_addr_r1 <= {31{1'bx}};
388 af_cmd_r1 <= {3{1'bx}};
389 end else if (~af_valid_r1 || sm_rden_r ||
391 af_valid_r1 <= af_valid_r;
392 af_addr_r1 <= af_addr_r;
393 af_cmd_r1 <= af_cmd_r;
397 // The state machine uses the address and command in this
398 // register stage. The data is fetched from the second
399 // register stage whenever the state machine can accept new
400 // addr. The conflict flags are also generated based on the
401 // second register stage and updated when the new address
402 // is loaded for the state machine.
403 always@(posedge clk) begin
406 af_addr_r2 <= {31{1'bx}};
407 af_cmd_r2 <= {3{1'bx}};
408 bank_hit_r <= {OPEN_BANK_NUM{1'bx}};
409 bank_conflict_r <= 1'bx;
410 row_conflict_r <= 4'bx;
411 end else if(sm_rden || ~af_valid_r2)begin
412 af_valid_r2 <= af_valid_r1;
413 af_addr_r2 <= af_addr_r1;
414 af_cmd_r2 <= af_cmd_r1;
415 if(MULTI_BANK_EN)begin
416 bank_hit_r <= bank_hit;
417 row_conflict_r <= row_miss;
418 bank_conflict_r <= (~(|bank_hit));
420 bank_hit_r <= {OPEN_BANK_NUM{1'b0}};
421 bank_conflict_r <= 1'd0;
422 row_conflict_r[0] <= (af_addr_r1[CS_RANGE_END:ROW_RANGE_START]
423 != sb_open_add_r[CMP_WIDTH-1:0]);
426 end // always@ (posedge clk)
428 //detecting cs change for multi chip select case
430 if(CS_NUM > 1) begin: gen_cs_change
431 always @(posedge clk) begin
432 if(sm_rden || ~af_valid_r2)begin
433 cs_change_r <= af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=
434 af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;
435 cs_change_sticky_r <=
436 af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=
437 af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;
441 end // block: gen_cs_change
443 always @(posedge clk) begin
445 cs_change_sticky_r <= 1'd0;
450 assign conflict_detect = (MULTI_BANK_EN) ?
451 ((|(row_conflict_r[3:0] & bank_hit_r[3:0]))
452 | bank_conflict_r) & af_valid_r2 :
453 row_conflict_r[0] & af_valid_r2;
455 always @(posedge clk) begin
456 conflict_detect_r <= conflict_detect;
457 sm_rden_r <= sm_rden;
458 af_addr_r3 <= af_addr_r2;
459 ctrl_af_rden_r <= ctrl_af_rden & ~af_empty;
462 // conflict resolved signal. When this signal is asserted
463 // the conflict is resolved. The address to be compared
464 // for the conflict_resolved_r will be stored in act_add_r
465 // when the bank is opened.
466 always @(posedge clk) begin
467 conflict_resolved_r <= (act_addr_r ==
468 af_addr_r2[CS_RANGE_END:ROW_RANGE_START]);
469 if((state_r == CTRL_ACTIVE))
470 act_addr_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];
473 //***************************************************************************
474 // Bank management logic
475 // Semi-hardcoded for now for 4 banks
476 // will keep multiple banks open if MULTI_BANK_EN is true.
477 //***************************************************************************
480 generate // if multiple bank option chosen
481 if(MULTI_BANK_EN) begin: gen_multi_bank_open
483 for (bank_i = 0; bank_i < OPEN_BANK_NUM;
484 bank_i = bank_i + 1) begin: gen_bank_hit1
485 // asserted if bank address match + open bank entry is valid
488 = ((bank_cmp_addr_r[(CMP_WIDTH*(bank_i+1))-1:
489 (CMP_WIDTH*bank_i)+ROW_WIDTH] ==
490 af_addr_r1[CS_RANGE_END:BANK_RANGE_START]) &&
491 bank_valid_r[bank_i]);
492 // asserted if row address match (no check for bank entry valid, rely
493 // on this term to be used in conjunction with BANK_HIT[])
495 = (bank_cmp_addr_r[(CMP_WIDTH*bank_i)+ROW_WIDTH-1:
496 (CMP_WIDTH*bank_i)] !=
497 af_addr_r1[ROW_RANGE_END:ROW_RANGE_START]);
501 always @(posedge clk) begin
502 no_precharge_wait_r <= bank_valid_r[3] & bank_conflict_r;
503 bank_hit_r1 <= bank_hit_r;
507 no_precharge_r = ~bank_valid_r[3] & bank_conflict_r;
510 no_precharge_r1 <= no_precharge_r;
513 always @(posedge clk) begin
514 // Clear all bank valid bits during AR (i.e. since all banks get
515 // precharged during auto-refresh)
516 if ((state_r1 == CTRL_AUTO_REFRESH)) begin
517 bank_valid_r <= {(OPEN_BANK_NUM-1){1'b0}};
518 bank_cmp_addr_r <= {(OPEN_BANK_NUM*CMP_WIDTH-1){1'b0}};
520 if (state_r1 == CTRL_ACTIVE) begin
521 // 00 is always going to have the latest bank and row.
522 bank_cmp_addr_r[CMP_WIDTH-1:0]
523 <= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];
524 // This indicates the bank was activated
525 bank_valid_r[0] <= 1'b1;
527 case ({bank_hit_r1[2:0]})
529 bank_cmp_addr_r[CMP_WIDTH-1:0]
530 <= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];
531 // This indicates the bank was activated
532 bank_valid_r[0] <= 1'b1;
534 3'b010: begin //(b0->b1)
535 bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
536 <= bank_cmp_addr_r[CMP_WIDTH-1:0];
537 bank_valid_r[1] <= bank_valid_r[0];
539 3'b100:begin //(b0->b1, b1->b2)
540 bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
541 <= bank_cmp_addr_r[CMP_WIDTH-1:0];
542 bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]
543 <= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];
544 bank_valid_r[1] <= bank_valid_r[0];
545 bank_valid_r[2] <= bank_valid_r[1];
547 default: begin //(b0->b1, b1->b2, b2->b3)
548 bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
549 <= bank_cmp_addr_r[CMP_WIDTH-1:0];
550 bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]
551 <= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];
552 bank_cmp_addr_r[(4*CMP_WIDTH)-1:3*CMP_WIDTH]
553 <= bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH];
554 bank_valid_r[1] <= bank_valid_r[0];
555 bank_valid_r[2] <= bank_valid_r[1];
556 bank_valid_r[3] <= bank_valid_r[2];
562 end else begin: gen_single_bank_open // single bank option
563 always @(posedge clk) begin
564 no_precharge_r <= 1'd0;
565 no_precharge_r1 <= 1'd0;
566 no_precharge_wait_r <= 1'd0;
568 sb_open_add_r <= {CMP_WIDTH{1'b0}};
569 else if (state_r == CTRL_ACTIVE)
570 sb_open_add_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];
575 //***************************************************************************
577 //***************************************************************************
579 //*****************************************************************
580 // Write and read enable generation for PHY
581 //*****************************************************************
583 // write burst count. Counts from (BL/2 to 1).
584 // Also logic for controller write enable.
585 always @(posedge clk) begin
586 if (state_r == CTRL_BURST_WRITE) begin
587 wrburst_cnt_r <= BURST_LEN_DIV2;
588 end else if (wrburst_cnt_r >= 3'd1)
589 wrburst_cnt_r <= wrburst_cnt_r - 1;
590 end // always @ (posedge clk)
593 always @(posedge clk) begin
596 end else if (state_r == CTRL_BURST_WRITE) begin
598 end else if (wrburst_wren_ok_r)
603 always @(posedge clk) begin
604 if ((state_r == CTRL_BURST_WRITE)
605 && (BURST_LEN_DIV2 > 2))
606 wrburst_ok_r <= 1'd0;
607 else if ((wrburst_cnt_r <= 3'd3) ||
608 (BURST_LEN_DIV2 <= 2))
609 wrburst_ok_r <= 1'b1;
612 // flag to check when wrburst count has reached
613 // a value of 1. This flag is used in the ctrl_wren
615 always @(posedge clk) begin
616 if(wrburst_cnt_r == 3'd2)
617 wrburst_wren_ok_r <=1'b1;
619 wrburst_wren_ok_r <= 1'b0;
623 // read burst count. Counts from (BL/2 to 1)
624 always @(posedge clk) begin
625 if (state_r == CTRL_BURST_READ) begin
626 rdburst_cnt_r <= BURST_LEN_DIV2;
627 end else if (rdburst_cnt_r >= 3'd1)
628 rdburst_cnt_r <= rdburst_cnt_r - 1;
629 end // always @ (posedge clk)
632 always @(posedge clk) begin
635 end else if (state_r == CTRL_BURST_READ) begin
637 end else if (rdburst_rden_ok_r)
641 // the rd_burst_ok_r signal will be asserted one cycle later
642 // in multi chip select cases if the back to back read is to
643 // different chip selects. The cs_changed_sticky_r signal will
644 // be asserted only for multi chip select cases.
645 always @(posedge clk) begin
646 if ((state_r == CTRL_BURST_READ)
647 && (BURST_LEN_DIV2 > 2))
648 rdburst_ok_r <= 1'd0;
649 else if ((rdburst_cnt_r <=( 3'd3 - cs_change_sticky_r)) ||
650 (BURST_LEN_DIV2 <= 2))
651 rdburst_ok_r <= 1'b1;
654 // flag to check when rdburst count has reached
655 // a value of 1. This flag is used in the ctrl_rden
657 always @(posedge clk) begin
658 if (rdburst_cnt_r == 3'd2)
659 rdburst_rden_ok_r <= 1'b1;
661 rdburst_rden_ok_r <= 1'b0;
665 //*****************************************************************
666 // Various delay counters
667 // The counters are checked for value of <= 3 to determine the
668 // if the count values are reached during different commands.
669 // It is checked for 3 because
670 // 1. The counters are loaded during the state when the command
671 // state is reached (+1)
672 // 2. After the <= 3 condition is reached the sm takes two cycles
673 // to transition to the new command state (+2)
674 //*****************************************************************
676 // tRP count - precharge command period
677 always @(posedge clk) begin
678 if (state_r == CTRL_PRECHARGE)
679 rp_cnt_r <= TRP_COUNT;
680 else if (rp_cnt_r != 4'd0)
681 rp_cnt_r <= rp_cnt_r - 1;
684 always @(posedge clk) begin
685 if (state_r == CTRL_PRECHARGE)
687 else if (rp_cnt_r <= 4'd3)
691 // tRFC count - refresh-refresh, refresh-active
692 always @(posedge clk) begin
693 if (state_r == CTRL_AUTO_REFRESH)
694 rfc_cnt_r <= TRFC_COUNT;
695 else if (rfc_cnt_r != 8'd0)
696 rfc_cnt_r <= rfc_cnt_r - 1;
699 always @(posedge clk) begin
700 if (state_r == CTRL_AUTO_REFRESH)
702 else if(rfc_cnt_r <= 8'd3)
706 // tRCD count - active to read/write
707 always @(posedge clk) begin
708 if (state_r == CTRL_ACTIVE)
709 rcd_cnt_r <= TRCD_COUNT;
710 else if (rcd_cnt_r != 4'd0)
711 rcd_cnt_r <= rcd_cnt_r - 1;
714 always @(posedge clk) begin
715 if ((state_r == CTRL_ACTIVE)
717 rcd_cnt_ok_r <= 1'd0;
718 else if (rcd_cnt_r <= 4'd3)
722 // tRRD count - active to active
723 always @(posedge clk) begin
724 if (state_r == CTRL_ACTIVE)
725 trrd_cnt_r <= TRRD_COUNT;
726 else if (trrd_cnt_r != 3'd0)
727 trrd_cnt_r <= trrd_cnt_r - 1;
730 always @(posedge clk) begin
731 if (state_r == CTRL_ACTIVE)
732 trrd_cnt_ok_r <= 1'd0;
733 else if (trrd_cnt_r <= 3'd3)
737 // tRAS count - active to precharge
738 always @(posedge clk) begin
739 if (state_r == CTRL_ACTIVE)
740 ras_cnt_r <= TRAS_COUNT;
741 else if (ras_cnt_r != 5'd0)
742 ras_cnt_r <= ras_cnt_r - 1;
745 // counter for write to prcharge
746 // read to precharge and
747 // activate to precharge
748 // precharge_ok_cnt_r is added with trtp count,
749 // there can be cases where the sm can go from
750 // activate to read and the act->pre count time
751 // would not have been satisfied. The rd->pre
752 // time is very less. wr->pre time is almost the
754 always @(posedge clk) begin
755 if (state_r == CTRL_BURST_READ) begin
756 // assign only if the cnt is < TRTP_COUNT
757 if (precharge_ok_cnt_r < TRTP_COUNT)
758 precharge_ok_cnt_r <= TRTP_COUNT;
759 end else if (state_r == CTRL_BURST_WRITE)
760 precharge_ok_cnt_r <= TWR_COUNT;
761 else if (state_r == CTRL_ACTIVE)
762 precharge_ok_cnt_r <= TRAS_COUNT;
763 else if (precharge_ok_cnt_r != 5'd0)
764 precharge_ok_cnt_r <= precharge_ok_cnt_r - 1;
767 always @(posedge clk) begin
768 if ((state_r == CTRL_BURST_READ) ||
769 (state_r == CTRL_BURST_WRITE)||
770 (state_r == CTRL_ACTIVE))
771 precharge_ok_r <= 1'd0;
772 else if(precharge_ok_cnt_r <= 5'd3)
773 precharge_ok_r <=1'd1;
776 // write to read counter
777 // write to read includes : write latency + burst time + tWTR
778 always @(posedge clk) begin
780 wr_to_rd_cnt_r <= 5'd0;
781 else if (state_r == CTRL_BURST_WRITE)
782 wr_to_rd_cnt_r <= (TWTR_COUNT);
783 else if (wr_to_rd_cnt_r != 5'd0)
784 wr_to_rd_cnt_r <= wr_to_rd_cnt_r - 1;
787 always @(posedge clk) begin
788 if (state_r == CTRL_BURST_WRITE)
789 wr_to_rd_ok_r <= 1'd0;
790 else if (wr_to_rd_cnt_r <= 5'd3)
791 wr_to_rd_ok_r <= 1'd1;
794 // read to write counter
795 always @(posedge clk) begin
797 rd_to_wr_cnt_r <= 5'd0;
798 else if (state_r == CTRL_BURST_READ)
799 rd_to_wr_cnt_r <= (TRTW_COUNT);
800 else if (rd_to_wr_cnt_r != 5'd0)
801 rd_to_wr_cnt_r <= rd_to_wr_cnt_r - 1;
804 always @(posedge clk) begin
805 if (state_r == CTRL_BURST_READ)
806 rd_to_wr_ok_r <= 1'b0;
807 else if (rd_to_wr_cnt_r <= 5'd3)
808 rd_to_wr_ok_r <= 1'b1;
811 always @(posedge clk) begin
812 if(refi_cnt_r == (TREFI_COUNT -1))
813 refi_cnt_ok_r <= 1'b1;
815 refi_cnt_ok_r <= 1'b0;
818 // auto refresh interval counter in refresh_clk domain
819 always @(posedge clk) begin
820 if ((rst_r1) || (refi_cnt_ok_r)) begin
823 refi_cnt_r <= refi_cnt_r + 1;
825 end // always @ (posedge clk)
828 always @(posedge clk) begin
829 if (refi_cnt_ok_r) begin
834 end // always @ (posedge clk)
836 assign ctrl_ref_flag = ref_flag_r;
838 //refresh flag detect
839 //auto_ref high indicates auto_refresh requirement
840 //auto_ref is held high until auto refresh command is issued.
841 always @(posedge clk)begin
846 else if (state_r == CTRL_AUTO_REFRESH)
851 // keep track of which chip selects got auto-refreshed (avoid auto-refreshing
852 // all CS's at once to avoid current spike)
853 always @(posedge clk)begin
854 if (rst_r1 || (state_r1 == CTRL_PRECHARGE))
856 else if (state_r1 == CTRL_AUTO_REFRESH)
857 auto_cnt_r <= auto_cnt_r + 1;
860 // register for timing purposes. Extra delay doesn't really matter
861 always @(posedge clk)
862 phy_init_done_r <= phy_init_done;
864 always @(posedge clk)begin
866 state_r <= CTRL_IDLE;
867 state_r1 <= CTRL_IDLE;
869 state_r <= next_state;
874 //***************************************************************************
875 // main control state machine
876 //***************************************************************************
879 next_state = state_r;
880 wr_fifo_burst = 1'b0;
882 (* full_case, parallel_case *) case (state_r)
884 // perform auto refresh as soon as we are done with calibration.
885 // The calibration logic does not do any refreshes.
887 next_state = CTRL_AUTO_REFRESH;
890 CTRL_PRECHARGE: begin
892 next_state = CTRL_PRECHARGE_WAIT1;
893 // when precharging an LRU bank, do not have to go to wait state
894 // since we can't possibly be activating row in same bank next
895 // disabled for 2t timing. There needs to be a gap between cmds
897 else if (no_precharge_wait_r && !TWO_T_TIME_EN)
898 next_state = CTRL_ACTIVE;
900 next_state = CTRL_PRECHARGE_WAIT;
903 CTRL_PRECHARGE_WAIT:begin
904 if (rp_cnt_ok_r)begin
906 // precharge again to make sure we close all the banks
907 next_state = CTRL_PRECHARGE;
909 next_state = CTRL_ACTIVE;
913 CTRL_PRECHARGE_WAIT1:
915 next_state = CTRL_AUTO_REFRESH;
918 next_state = CTRL_AUTO_REFRESH_WAIT;
920 CTRL_AUTO_REFRESH_WAIT:
921 //staggering Auto refresh for multi
922 // chip select designs. The SM waits
923 // for the rfc time before issuing the
924 // next auto refresh.
925 if (auto_cnt_r < (CS_NUM))begin
927 next_state = CTRL_AUTO_REFRESH;
928 end else if (rfc_ok_r)begin
930 // MIG 2.3: For deep designs if Auto Refresh
931 // flag asserted immediately after calibration is completed
932 next_state = CTRL_PRECHARGE;
933 else if ( wr_flag || rd_flag)
934 next_state = CTRL_ACTIVE;
938 next_state = CTRL_ACTIVE_WAIT;
940 CTRL_ACTIVE_WAIT: begin
941 if (rcd_cnt_ok_r) begin
942 if ((conflict_detect_r && ~conflict_resolved_r) ||
944 if (no_precharge_r1 && ~auto_ref_r && trrd_cnt_ok_r)
945 next_state = CTRL_ACTIVE;
946 else if(precharge_ok_r)
947 next_state = CTRL_PRECHARGE;
948 end else if ((wr_flag_r) && (rd_to_wr_ok_r) && wr_fifo_clear) begin
949 next_state = CTRL_BURST_WRITE;
950 wr_fifo_burst = 1'b1;
951 end else if ((rd_flag_r)&& (wr_to_rd_ok_r) && rd_fifo_clear)
952 next_state = CTRL_BURST_READ;
956 // beginning of write burst
957 CTRL_BURST_WRITE: begin
958 if (BURST_LEN_DIV2 == 1) begin
959 // special case if BL = 2 (i.e. burst lasts only one clk cycle)
960 if (wr_flag && wr_fifo_clear) begin
961 // if we have another non-conflict write command right after the
962 // current write, then stay in this state
963 next_state = CTRL_BURST_WRITE;
964 wr_fifo_burst = 1'b1;
966 // otherwise, if we're done with this burst, and have no write
967 // immediately scheduled after this one, wait until write-read
969 next_state = CTRL_WRITE_WAIT;
971 // otherwise BL > 2, and we have at least one more write cycle for
973 next_state = CTRL_WRITE_WAIT;
974 // continuation of write burst (also covers waiting after write burst
975 // has completed for write-read delay to pass)
978 CTRL_WRITE_WAIT: begin
979 if ((conflict_detect) || auto_ref_r) begin
980 if (no_precharge_r && ~auto_ref_r && wrburst_ok_r)
981 next_state = CTRL_ACTIVE;
982 else if (precharge_ok_r)
983 next_state = CTRL_PRECHARGE;
984 end else if (wrburst_ok_r && wr_flag && wr_fifo_clear) begin
985 next_state = CTRL_BURST_WRITE;
986 wr_fifo_burst = 1'b1;
987 end else if ((rd_flag) && (wr_to_rd_ok_r) && rd_fifo_clear)
988 next_state = CTRL_BURST_READ;
991 CTRL_BURST_READ: begin
992 if (BURST_LEN_DIV2 == 1) begin
993 // special case if BL = 2 (i.e. burst lasts only one clk cycle)
994 if (rd_flag && rd_fifo_clear)
995 next_state = CTRL_BURST_READ;
997 next_state = CTRL_READ_WAIT;
999 next_state = CTRL_READ_WAIT;
1002 CTRL_READ_WAIT: begin
1003 if ((conflict_detect) || auto_ref_r)begin
1004 if (no_precharge_r && ~auto_ref_r && rdburst_ok_r)
1005 next_state = CTRL_ACTIVE;
1006 else if (precharge_ok_r)
1007 next_state = CTRL_PRECHARGE;
1008 // for burst of 4 in multi chip select
1009 // if there is a change in cs wait one cycle before the
1010 // next read command. cs_change_r will be asserted.
1011 end else if (rdburst_ok_r && rd_flag && ~cs_change_r && rd_fifo_clear)
1012 next_state = CTRL_BURST_READ;
1013 else if (wr_flag && (rd_to_wr_ok_r) && wr_fifo_clear) begin
1014 next_state = CTRL_BURST_WRITE;
1015 wr_fifo_burst = 1'b1;
1021 //***************************************************************************
1022 // control signals to memory
1023 //***************************************************************************
1025 always @(posedge clk) begin
1026 if ((state_r == CTRL_AUTO_REFRESH) ||
1027 (state_r == CTRL_ACTIVE) ||
1028 (state_r == CTRL_PRECHARGE)) begin
1029 ddr_ras_n_r <= 1'b0;
1030 two_t_enable_r[0] <= 1'b0;
1033 ddr_ras_n_r <= two_t_enable_r[0] ;
1035 ddr_ras_n_r <= 1'd1;
1036 two_t_enable_r[0] <= 1'b1;
1040 always @(posedge clk)begin
1041 if ((state_r == CTRL_BURST_WRITE) ||
1042 (state_r == CTRL_BURST_READ) ||
1043 (state_r == CTRL_AUTO_REFRESH)) begin
1044 ddr_cas_n_r <= 1'b0;
1045 two_t_enable_r[1] <= 1'b0;
1048 ddr_cas_n_r <= two_t_enable_r[1];
1050 ddr_cas_n_r <= 1'b1;
1051 two_t_enable_r[1] <= 1'b1;
1055 always @(posedge clk) begin
1056 if ((state_r == CTRL_BURST_WRITE) ||
1057 (state_r == CTRL_PRECHARGE)) begin
1059 two_t_enable_r[2] <= 1'b0;
1062 ddr_we_n_r <= two_t_enable_r[2];
1065 two_t_enable_r[2] <= 1'b1;
1069 // turn off auto-precharge when issuing commands (A10 = 0)
1070 // mapping the col add for linear addressing.
1072 if (TWO_T_TIME_EN) begin: gen_addr_col_two_t
1073 if (COL_WIDTH == ROW_WIDTH-1) begin: gen_ddr_addr_col_0
1074 assign ddr_addr_col = {af_addr_r3[COL_WIDTH-1:10], 1'b0,
1077 if (COL_WIDTH > 10) begin: gen_ddr_addr_col_1
1078 assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}},
1079 af_addr_r3[COL_WIDTH-1:10], 1'b0,
1081 end else begin: gen_ddr_addr_col_2
1082 assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}}, 1'b0,
1083 af_addr_r3[COL_WIDTH-1:0]};
1086 end else begin: gen_addr_col_one_t
1087 if (COL_WIDTH == ROW_WIDTH-1) begin: gen_ddr_addr_col_0_1
1088 assign ddr_addr_col = {af_addr_r2[COL_WIDTH-1:10], 1'b0,
1091 if (COL_WIDTH > 10) begin: gen_ddr_addr_col_1_1
1092 assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}},
1093 af_addr_r2[COL_WIDTH-1:10], 1'b0,
1095 end else begin: gen_ddr_addr_col_2_1
1096 assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}}, 1'b0,
1097 af_addr_r2[COL_WIDTH-1:0]};
1103 // Assign address during row activate
1106 assign ddr_addr_row = af_addr_r3[ROW_RANGE_END:ROW_RANGE_START];
1108 assign ddr_addr_row = af_addr_r2[ROW_RANGE_END:ROW_RANGE_START];
1112 always @(posedge clk)begin
1113 if ((state_r == CTRL_ACTIVE) ||
1114 ((state_r1 == CTRL_ACTIVE) && TWO_T_TIME_EN))
1115 ddr_addr_r <= ddr_addr_row;
1116 else if ((state_r == CTRL_BURST_WRITE) ||
1117 (state_r == CTRL_BURST_READ) ||
1118 (((state_r1 == CTRL_BURST_WRITE) ||
1119 (state_r1 == CTRL_BURST_READ)) &&
1121 ddr_addr_r <= ddr_addr_col;
1122 else if (((state_r == CTRL_PRECHARGE) ||
1123 ((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN))
1124 && auto_ref_r) begin
1125 // if we're precharging as a result of AUTO-REFRESH, precharge all banks
1126 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1127 ddr_addr_r[10] <= 1'b1;
1128 end else if ((state_r == CTRL_PRECHARGE) ||
1129 ((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN))
1130 // if we're precharging to close a specific bank/row, set A10=0
1131 ddr_addr_r <= {ROW_WIDTH{1'b0}};
1133 ddr_addr_r <= {ROW_WIDTH{1'bx}};
1136 always @(posedge clk)begin
1137 // whenever we're precharging, we're either: (1) precharging all banks (in
1138 // which case banks bits are don't care, (2) precharging the LRU bank,
1139 // b/c we've exceeded the limit of # of banks open (need to close the LRU
1140 // bank to make room for a new one), (3) we haven't exceed the maximum #
1141 // of banks open, but we trying to open a different row in a bank that's
1143 if (((state_r == CTRL_PRECHARGE) ||
1144 ((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN)) &&
1145 bank_conflict_r && MULTI_BANK_EN)
1146 // When LRU bank needs to be closed
1147 ddr_ba_r <= bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_BANK_RANGE_END:
1148 (3*CMP_WIDTH)+CMP_BANK_RANGE_START];
1150 // Either precharge due to refresh or bank hit case
1152 ddr_ba_r <= af_addr_r3[BANK_RANGE_END:BANK_RANGE_START];
1154 ddr_ba_r <= af_addr_r2[BANK_RANGE_END:BANK_RANGE_START];
1158 // chip enable generation logic
1160 // if only one chip select, always assert it after reset
1161 if (CS_BITS == 0) begin: gen_ddr_cs_0
1162 always @(posedge clk)
1164 ddr_cs_n_r[0] <= 1'b1;
1166 ddr_cs_n_r[0] <= 1'b0;
1167 // otherwise if we have multiple chip selects
1168 end else begin: gen_ddr_cs_1
1169 if(TWO_T_TIME_EN) begin: gen_2t_cs
1170 always @(posedge clk)
1172 ddr_cs_n_r <= {CS_NUM{1'b1}};
1173 else if ((state_r1 == CTRL_AUTO_REFRESH)) begin
1174 // if auto-refreshing, only auto-refresh one CS at any time (avoid
1175 // beating on the ground plane by refreshing all CS's at same time)
1176 ddr_cs_n_r <= {CS_NUM{1'b1}};
1177 ddr_cs_n_r[auto_cnt_r] <= 1'b0;
1178 end else if (auto_ref_r && (state_r1 == CTRL_PRECHARGE)) begin
1179 ddr_cs_n_r <= {CS_NUM{1'b0}};
1180 end else if ((state_r1 == CTRL_PRECHARGE) && ( bank_conflict_r
1181 && MULTI_BANK_EN))begin
1182 // precharging the LRU bank
1183 ddr_cs_n_r <= {CS_NUM{1'b1}};
1184 ddr_cs_n_r[bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_CS_RANGE_END:
1185 (3*CMP_WIDTH)+CMP_CS_RANGE_START]] <= 1'b0;
1187 // otherwise, check the upper address bits to see which CS to assert
1188 ddr_cs_n_r <= {CS_NUM{1'b1}};
1189 ddr_cs_n_r[af_addr_r3[CS_RANGE_END:CS_RANGE_START]] <= 1'b0;
1190 end // else: !if(((state_r == CTRL_PRECHARGE) ||...
1191 end else begin: gen_1t_cs // block: gen_2t_cs
1192 always @(posedge clk)
1194 ddr_cs_n_r <= {CS_NUM{1'b1}};
1195 else if ((state_r == CTRL_AUTO_REFRESH) ) begin
1196 // if auto-refreshing, only auto-refresh one CS at any time (avoid
1197 // beating on the ground plane by refreshing all CS's at same time)
1198 ddr_cs_n_r <= {CS_NUM{1'b1}};
1199 ddr_cs_n_r[auto_cnt_r] <= 1'b0;
1200 end else if (auto_ref_r && (state_r == CTRL_PRECHARGE) ) begin
1201 ddr_cs_n_r <= {CS_NUM{1'b0}};
1202 end else if ((state_r == CTRL_PRECHARGE) &&
1203 (bank_conflict_r && MULTI_BANK_EN))begin
1204 // precharging the LRU bank
1205 ddr_cs_n_r <= {CS_NUM{1'b1}};
1206 ddr_cs_n_r[bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_CS_RANGE_END:
1207 (3*CMP_WIDTH)+CMP_CS_RANGE_START]] <= 1'b0;
1209 // otherwise, check the upper address bits to see which CS to assert
1210 ddr_cs_n_r <= {CS_NUM{1'b1}};
1211 ddr_cs_n_r[af_addr_r2[CS_RANGE_END:CS_RANGE_START]] <= 1'b0;
1212 end // else: !if(((state_r == CTRL_PRECHARGE) ||...
1213 end // block: gen_1t_cs
1217 // registring the two_t timing enable signal.
1218 // This signal will be asserted (low) when the
1219 // chip select has to be asserted.
1220 always @(posedge clk)begin
1222 two_t_enable_r1 <= {CS_NUM{1'b1}};
1224 two_t_enable_r1 <= {CS_NUM{1'b0}};
1227 assign ctrl_addr = ddr_addr_r;
1228 assign ctrl_ba = ddr_ba_r;
1229 assign ctrl_ras_n = ddr_ras_n_r;
1230 assign ctrl_cas_n = ddr_cas_n_r;
1231 assign ctrl_we_n = ddr_we_n_r;
1232 assign ctrl_cs_n = (TWO_T_TIME_EN) ?
1233 (ddr_cs_n_r | two_t_enable_r1) :