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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_infrastructure.v
50 // /___/ /\ Date Last Modified: $Date: 2008/05/08 15:20:47 $
51 // \ \ / \ Date Created: Wed Aug 16 2006
57 // Clock distribution and reset synchronization
60 //*****************************************************************************
64 module ddr2_infrastructure #
66 parameter RST_ACT_LOW = 1
75 input idelay_ctrl_rdy,
82 // # of clock cycles to delay deassertion of reset. Needs to be a fairly
83 // high number not so much for metastability protection, but to give time
84 // for reset (i.e. stable clock cycles) to propagate through all state
85 // machines and to all control signals (i.e. not all control signals have
86 // resets, instead they rely on base state logic being reset, and the effect
87 // of that reset propagating through the logic). Need this because we may not
88 // be getting stable clock cycles while reset asserted (i.e. since reset
89 // depends on DCM lock status)
90 localparam RST_SYNC_NUM = 25;
92 reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
93 reg [RST_SYNC_NUM-1:0] rst200_sync_r /* synthesis syn_maxfan = 10 */;
94 reg [RST_SYNC_NUM-1:0] rst90_sync_r /* synthesis syn_maxfan = 10 */;
95 reg [(RST_SYNC_NUM/2)-1:0] rstdiv0_sync_r /* synthesis syn_maxfan = 10 */;
100 assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;
104 //***************************************************************************
105 // Reset synchronization
107 // 1. shut down the whole operation if the DCM hasn't yet locked (and by
108 // inference, this means that external SYS_RST_IN has been asserted -
109 // DCM deasserts DCM_LOCK as soon as SYS_RST_IN asserted)
110 // 2. In the case of all resets except rst200, also assert reset if the
111 // IDELAY master controller is not yet ready
112 // 3. asynchronously assert reset. This was we can assert reset even if
113 // there is no clock (needed for things like 3-stating output buffers).
114 // reset deassertion is synchronous.
115 //***************************************************************************
117 assign rst_tmp = sys_rst | ~dcm_lock | ~idelay_ctrl_rdy;
119 // synthesis attribute max_fanout of rst0_sync_r is 10
120 always @(posedge clk0 or posedge rst_tmp)
122 rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
124 // logical left shift by one (pads with 0)
125 rst0_sync_r <= rst0_sync_r << 1;
127 // synthesis attribute max_fanout of rstdiv0_sync_r is 10
128 always @(posedge clkdiv0 or posedge rst_tmp)
130 rstdiv0_sync_r <= {(RST_SYNC_NUM/2){1'b1}};
132 // logical left shift by one (pads with 0)
133 rstdiv0_sync_r <= rstdiv0_sync_r << 1;
135 // synthesis attribute max_fanout of rst90_sync_r is 10
136 always @(posedge clk90 or posedge rst_tmp)
138 rst90_sync_r <= {RST_SYNC_NUM{1'b1}};
140 rst90_sync_r <= rst90_sync_r << 1;
142 // make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg
143 // synthesis attribute max_fanout of rst200_sync_r is 10
144 always @(posedge clk200 or negedge dcm_lock)
146 rst200_sync_r <= {RST_SYNC_NUM{1'b1}};
148 rst200_sync_r <= rst200_sync_r << 1;
151 assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
152 assign rst90 = rst90_sync_r[RST_SYNC_NUM-1];
153 assign rst200 = rst200_sync_r[RST_SYNC_NUM-1];
154 assign rstdiv0 = rstdiv0_sync_r[(RST_SYNC_NUM/2)-1];