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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_phy_ctl_io.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/29 15:24:03 $
51 // \ \ / \ Date Created: Thu Aug 24 2006
57 // This module puts the memory control signals like address, bank address,
58 // row address strobe, column address strobe, write enable and clock enable
62 //*****************************************************************************
66 module ddr2_phy_ctl_io #
68 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
69 // board design). Actual values may be different. Actual parameters values
70 // are passed from design top module ddr2_sdram module. Please refer to
71 // the ddr2_sdram module for actual values.
72 parameter BANK_WIDTH = 2,
73 parameter CKE_WIDTH = 1,
74 parameter COL_WIDTH = 10,
76 parameter TWO_T_TIME_EN = 0,
77 parameter CS_WIDTH = 1,
78 parameter ODT_WIDTH = 1,
79 parameter ROW_WIDTH = 14,
80 parameter DDR_TYPE = 1
87 input [ROW_WIDTH-1:0] ctrl_addr,
88 input [BANK_WIDTH-1:0] ctrl_ba,
92 input [CS_NUM-1:0] ctrl_cs_n,
93 input [ROW_WIDTH-1:0] phy_init_addr,
94 input [BANK_WIDTH-1:0] phy_init_ba,
98 input [CS_NUM-1:0] phy_init_cs_n,
99 input [CKE_WIDTH-1:0] phy_init_cke,
100 input phy_init_data_sel,
101 input [CS_NUM-1:0] odt,
102 output [ROW_WIDTH-1:0] ddr_addr,
103 output [BANK_WIDTH-1:0] ddr_ba,
107 output [CKE_WIDTH-1:0] ddr_cke,
108 output [CS_WIDTH-1:0] ddr_cs_n,
109 output [ODT_WIDTH-1:0] ddr_odt
112 reg [ROW_WIDTH-1:0] addr_mux;
113 reg [BANK_WIDTH-1:0] ba_mux;
115 reg [CS_NUM-1:0] cs_n_mux;
121 //***************************************************************************
126 // MUX to choose from either PHY or controller for SDRAM control
128 generate // in 2t timing mode the extra register stage cannot be used.
129 if(TWO_T_TIME_EN) begin // the control signals are asserted for two cycles
131 if (phy_init_data_sel) begin
132 addr_mux = ctrl_addr;
134 cas_n_mux = ctrl_cas_n;
135 cs_n_mux = ctrl_cs_n;
136 ras_n_mux = ctrl_ras_n;
137 we_n_mux = ctrl_we_n;
139 addr_mux = phy_init_addr;
140 ba_mux = phy_init_ba;
141 cas_n_mux = phy_init_cas_n;
142 cs_n_mux = phy_init_cs_n;
143 ras_n_mux = phy_init_ras_n;
144 we_n_mux = phy_init_we_n;
148 always @(posedge clk0)begin // register the signals in non 2t mode
149 if (phy_init_data_sel) begin
150 addr_mux <= ctrl_addr;
152 cas_n_mux <= ctrl_cas_n;
153 cs_n_mux <= ctrl_cs_n;
154 ras_n_mux <= ctrl_ras_n;
155 we_n_mux <= ctrl_we_n;
157 addr_mux <= phy_init_addr;
158 ba_mux <= phy_init_ba;
159 cas_n_mux <= phy_init_cas_n;
160 cs_n_mux <= phy_init_cs_n;
161 ras_n_mux <= phy_init_ras_n;
162 we_n_mux <= phy_init_we_n;
168 //***************************************************************************
169 // Output flop instantiation
170 // NOTE: Make sure all control/address flops are placed in IOBs
171 //***************************************************************************
174 (* IOB = "TRUE" *) FDCPE u_ff_ras_n
182 ) /* synthesis syn_useioff = 1 */;
185 (* IOB = "TRUE" *) FDCPE u_ff_cas_n
193 ) /* synthesis syn_useioff = 1 */;
196 (* IOB = "TRUE" *) FDCPE u_ff_we_n
204 ) /* synthesis syn_useioff = 1 */;
209 for (cke_i = 0; cke_i < CKE_WIDTH; cke_i = cke_i + 1) begin: gen_cke
210 (* IOB = "TRUE" *) FDCPE u_ff_cke
216 .D (phy_init_cke[cke_i]),
218 ) /* synthesis syn_useioff = 1 */;
222 // chip select: = 1 at reset
223 // For unbuffered dimms the loading will be high. The chip select
224 // can be asserted early if the loading is very high. The
225 // code as is uses clock 0. If needed clock 270 can be used to
226 // toggle chip select 1/4 clock cycle early. The code has
227 // the clock 90 input for the early assertion of chip select.
231 for(cs_i = 0; cs_i < CS_WIDTH; cs_i = cs_i + 1) begin: gen_cs_n
232 if(TWO_T_TIME_EN) begin
233 (* IOB = "TRUE" *) FDCPE u_ff_cs_n
239 .D (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
241 ) /* synthesis syn_useioff = 1 */;
242 end else begin // if (TWO_T_TIME_EN)
243 (* IOB = "TRUE" *) FDCPE u_ff_cs_n
249 .D (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
251 ) /* synthesis syn_useioff = 1 */;
252 end // else: !if(TWO_T_TIME_EN)
256 // address: = X at reset
259 for (addr_i = 0; addr_i < ROW_WIDTH; addr_i = addr_i + 1) begin: gen_addr
260 (* IOB = "TRUE" *) FDCPE u_ff_addr
262 .Q (ddr_addr[addr_i]),
266 .D (addr_mux[addr_i]),
268 ) /* synthesis syn_useioff = 1 */;
272 // bank address = X at reset
275 for (ba_i = 0; ba_i < BANK_WIDTH; ba_i = ba_i + 1) begin: gen_ba
276 (* IOB = "TRUE" *) FDCPE u_ff_ba
284 ) /* synthesis syn_useioff = 1 */;
288 // ODT control = 0 at reset
291 if (DDR_TYPE > 0) begin: gen_odt_ddr2
292 for (odt_i = 0; odt_i < ODT_WIDTH; odt_i = odt_i + 1) begin: gen_odt
293 (* IOB = "TRUE" *) FDCPE u_ff_odt
299 .D (odt[(odt_i*CS_NUM)/ODT_WIDTH]),
301 ) /* synthesis syn_useioff = 1 */;