1 //*****************************************************************************
2 // DISCLAIMER OF LIABILITY
4 // This text/file contains proprietary, confidential
5 // information of Xilinx, Inc., is distributed under license
6 // from Xilinx, Inc., and may be used, copied and/or
7 // disclosed only pursuant to the terms of a valid license
8 // agreement with Xilinx, Inc. Xilinx hereby grants you a
9 // license to use this text/file solely for design, simulation,
10 // implementation and creation of design files limited
11 // to Xilinx devices or technologies. Use with non-Xilinx
12 // devices or technologies is expressly prohibited and
13 // immediately terminates your license unless covered by
14 // a separate agreement.
16 // Xilinx is providing this design, code, or information
17 // "as-is" solely for use in developing programs and
18 // solutions for Xilinx devices, with no obligation on the
19 // part of Xilinx to provide support. By providing this design,
20 // code, or information as one possible implementation of
21 // this feature, application or standard, Xilinx is making no
22 // representation that this implementation is free from any
23 // claims of infringement. You are responsible for
24 // obtaining any rights you may require for your implementation.
25 // Xilinx expressly disclaims any warranty whatsoever with
26 // respect to the adequacy of the implementation, including
27 // but not limited to any warranties or representations that this
28 // implementation is free from claims of infringement, implied
29 // warranties of merchantability or fitness for a particular
32 // Xilinx products are not intended for use in life support
33 // appliances, devices, or systems. Use in such applications is
34 // expressly prohibited.
36 // Any modifications that are made to the Source Code are
37 // done at the user
\92s sole risk and will be unsupported.
39 // Copyright (c) 2006-2007 Xilinx, Inc. All rights reserved.
41 // This copyright and support notice must be retained as part
42 // of this text at all times.
43 //*****************************************************************************
46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_sdram.v
50 // /___/ /\ Date Last Modified: $Date: 2008/07/09 12:33:12 $
51 // \ \ / \ Date Created: Wed Aug 16 2006
57 // Top-level module. Simple model for what the user might use
58 // Typically, the user will only instantiate MEM_INTERFACE_TOP in their
59 // code, and generate all backend logic (test bench) and all the other infrastructure logic
61 // In addition to the memory controller, the module instantiates:
62 // 1. Reset logic based on user clocks
63 // 2. IDELAY control block
66 //*****************************************************************************
70 (* X_CORE_INFO = "mig_v2_3_ddr2_sdram_v5, Coregen 10.1.02" , CORE_GENERATION_INFO = "ddr2_sdram_v5,mig_v2_3,{component_name=ddr2_sdram, BANK_WIDTH=2, CKE_WIDTH=1, CLK_WIDTH=2, COL_WIDTH=10, CS_NUM=1, CS_WIDTH=1, DM_WIDTH=8, DQ_WIDTH=64, DQ_PER_DQS=8, DQS_WIDTH=8, ODT_WIDTH=1, ROW_WIDTH=13, ADDITIVE_LAT=0, BURST_LEN=4, BURST_TYPE=0, CAS_LAT=4, ECC_ENABLE=0, MULTI_BANK_EN=1, TWO_T_TIME_EN=1, ODT_TYPE=1, REDUCE_DRV=0, REG_ENABLE=0, TREFI_NS=7800, TRAS=40000, TRCD=15000, TRFC=105000, TRP=15000, TRTP=7500, TWR=15000, TWTR=7500, DDR2_CLK_PERIOD=3750, RST_ACT_LOW=1}" *)
73 parameter BANK_WIDTH = 2,
74 // # of memory bank addr bits.
75 parameter CKE_WIDTH = 1,
76 // # of memory clock enable outputs.
77 parameter CLK_WIDTH = 2,
78 // # of clock outputs.
79 parameter COL_WIDTH = 10,
80 // # of memory column bits.
82 // # of separate memory chip selects.
83 parameter CS_WIDTH = 1,
84 // # of total memory chip selects.
85 parameter CS_BITS = 0,
86 // set to log2(CS_NUM) (rounded up).
87 parameter DM_WIDTH = 8,
88 // # of data mask bits.
89 parameter DQ_WIDTH = 64,
91 parameter DQ_PER_DQS = 8,
92 // # of DQ data bits per strobe.
93 parameter DQS_WIDTH = 8,
95 parameter DQ_BITS = 6,
96 // set to log2(DQS_WIDTH*DQ_PER_DQS).
97 parameter DQS_BITS = 3,
98 // set to log2(DQS_WIDTH).
99 parameter ODT_WIDTH = 1,
100 // # of memory on-die term enables.
101 parameter ROW_WIDTH = 13,
102 // # of memory row and # of addr bits.
103 parameter ADDITIVE_LAT = 0,
104 // additive write latency.
105 parameter BURST_LEN = 4,
106 // burst length (in double words).
107 parameter BURST_TYPE = 0,
108 // burst type (=0 seq; =1 interleaved).
109 parameter CAS_LAT = 4,
111 parameter ECC_ENABLE = 0,
112 // enable ECC (=1 enable).
113 parameter APPDATA_WIDTH = 128,
114 // # of usr read/write data bus bits.
115 parameter MULTI_BANK_EN = 1,
116 // Keeps multiple banks open. (= 1 enable).
117 parameter TWO_T_TIME_EN = 1,
118 // 2t timing for unbuffered dimms.
119 parameter ODT_TYPE = 1,
120 // ODT (=0(none),=1(75),=2(150),=3(50)).
121 parameter REDUCE_DRV = 0,
122 // reduced strength mem I/O (=1 yes).
123 parameter REG_ENABLE = 0,
124 // registered addr/ctrl (=1 yes).
125 parameter TREFI_NS = 7800,
126 // auto refresh interval (ns).
127 parameter TRAS = 40000,
128 // active->precharge delay.
129 parameter TRCD = 15000,
130 // active->read/write delay.
131 parameter TRFC = 105000,
132 // refresh->refresh, refresh->active delay.
133 parameter TRP = 15000,
134 // precharge->command delay.
135 parameter TRTP = 7500,
136 // read->precharge delay.
137 parameter TWR = 15000,
138 // used to determine write->precharge.
139 parameter TWTR = 7500,
140 // write->read delay.
141 parameter HIGH_PERFORMANCE_MODE = "TRUE",
142 // # = TRUE, the IODELAY performance mode is set
144 // # = FALSE, the IODELAY performance mode is set
146 parameter SIM_ONLY = 0,
147 // = 1 to skip SDRAM power up delay.
148 parameter DEBUG_EN = 0,
149 // Enable debug signals/controls.
150 // When this parameter is changed from 0 to 1,
151 // make sure to uncomment the coregen commands
152 // in ise_flow.bat or create_ise.bat files in
154 parameter CLK_PERIOD = 3750,
155 // Core/Memory clock period (in ps).
156 parameter DQS_IO_COL = 16'b0000000000000000,
157 // I/O column location of DQS groups
158 // (=0, left; =1 center, =2 right).
159 parameter DQ_IO_MS = 64'b01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100,
160 // Master/Slave location of DQ I/O (=0 slave).
161 parameter RST_ACT_LOW = 1,
162 // =1 for active low reset, =0 for active high.
163 parameter EN_SYN = "FALSE"
166 inout [DQ_WIDTH-1:0] ddr2_dq,
167 output [ROW_WIDTH-1:0] ddr2_a,
168 output [BANK_WIDTH-1:0] ddr2_ba,
172 output [CS_WIDTH-1:0] ddr2_cs_n,
173 output [ODT_WIDTH-1:0] ddr2_odt,
174 output [CKE_WIDTH-1:0] ddr2_cke,
175 output [DM_WIDTH-1:0] ddr2_dm,
177 output phy_init_done,
186 //added by xtan & gdgib
187 input af_clk, //address fifo clk
188 input rb_clk, //read buffer clk
189 input wb_clk, //write buffer clk
190 input af_rst, //address fifo rst
191 input rb_rst, //read buffer rst
192 input wb_rst, //write buffer rst
193 output rb_full, //read buffer is full
196 output app_wdf_afull,
198 output rd_data_valid,
201 input [30:0] app_af_addr,
202 input [2:0] app_af_cmd,
203 output [(APPDATA_WIDTH)-1:0] rd_data_fifo_out,
205 output [1:0] rd_ecc_error,
206 input [(APPDATA_WIDTH)-1:0] app_wdf_data,
207 input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
208 inout [DQS_WIDTH-1:0] ddr2_dqs,
209 inout [DQS_WIDTH-1:0] ddr2_dqs_n,
210 output [CLK_WIDTH-1:0] ddr2_ck,
211 output [CLK_WIDTH-1:0] ddr2_ck_n
214 /////////////////////////////////////////////////////////////////////////////
215 // The following parameter "IDELAYCTRL_NUM" indicates the number of
216 // IDELAYCTRLs that are LOCed for the design. The IDELAYCTRL LOCs are
217 // provided in the UCF file of par folder. MIG provides the parameter value
218 // and the LOCs in the UCF file based on the selected Data Read banks for
219 // the design. You must not alter this value unless it is needed. If you
220 // modify this value, you should make sure that the value of "IDELAYCTRL_NUM"
221 // and IDELAYCTRL LOCs in UCF file are same and are relavent to the Data Read
223 /////////////////////////////////////////////////////////////////////////////
225 localparam IDELAYCTRL_NUM = 3;
235 wire idelay_ctrl_rdy;
241 wire [3:0] dbg_calib_done;
242 wire [3:0] dbg_calib_err;
243 wire [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt;
244 wire [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt;
245 wire [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt;
246 wire [DQS_WIDTH-1:0] dbg_calib_rd_data_sel;
247 wire [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly;
248 wire [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly;
249 wire dbg_idel_up_all;
250 wire dbg_idel_down_all;
252 wire dbg_idel_down_dq;
253 wire dbg_idel_up_dqs;
254 wire dbg_idel_down_dqs;
255 wire dbg_idel_up_gate;
256 wire dbg_idel_down_gate;
257 wire [DQ_BITS-1:0] dbg_sel_idel_dq;
258 wire dbg_sel_all_idel_dq;
259 wire [DQS_BITS:0] dbg_sel_idel_dqs;
260 wire dbg_sel_all_idel_dqs;
261 wire [DQS_BITS:0] dbg_sel_idel_gate;
262 wire dbg_sel_all_idel_gate;
265 // Debug signals (optional use)
267 //***********************************
268 // PHY Debug Port demo
269 //***********************************
270 wire [35:0] cs_control0;
271 wire [35:0] cs_control1;
272 wire [35:0] cs_control2;
273 wire [35:0] cs_control3;
274 wire [191:0] vio0_in;
277 wire [31:0] vio3_out;
281 //***************************************************************************
283 assign rst0_tb = rst0;
284 assign clk0_tb = clk0;
289 .IDELAYCTRL_NUM (IDELAYCTRL_NUM)
295 .idelay_ctrl_rdy (idelay_ctrl_rdy)
298 ddr2_infrastructure #
300 .RST_ACT_LOW (RST_ACT_LOW)
302 u_ddr2_infrastructure
304 .sys_rst_n (sys_rst_n),
305 .dcm_lock (dcm_lock),
314 .idelay_ctrl_rdy (idelay_ctrl_rdy)
319 .BANK_WIDTH (BANK_WIDTH),
320 .CKE_WIDTH (CKE_WIDTH),
321 .CLK_WIDTH (CLK_WIDTH),
322 .COL_WIDTH (COL_WIDTH),
324 .CS_WIDTH (CS_WIDTH),
326 .DM_WIDTH (DM_WIDTH),
327 .DQ_WIDTH (DQ_WIDTH),
328 .DQ_PER_DQS (DQ_PER_DQS),
329 .DQS_WIDTH (DQS_WIDTH),
331 .DQS_BITS (DQS_BITS),
332 .ODT_WIDTH (ODT_WIDTH),
333 .ROW_WIDTH (ROW_WIDTH),
334 .ADDITIVE_LAT (ADDITIVE_LAT),
335 .BURST_LEN (BURST_LEN),
336 .BURST_TYPE (BURST_TYPE),
338 .ECC_ENABLE (ECC_ENABLE),
339 .APPDATA_WIDTH (APPDATA_WIDTH),
340 .MULTI_BANK_EN (MULTI_BANK_EN),
341 .TWO_T_TIME_EN (TWO_T_TIME_EN),
342 .ODT_TYPE (ODT_TYPE),
343 .REDUCE_DRV (REDUCE_DRV),
344 .REG_ENABLE (REG_ENABLE),
345 .TREFI_NS (TREFI_NS),
353 .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
354 .SIM_ONLY (SIM_ONLY),
355 .DEBUG_EN (DEBUG_EN),
356 .CLK_PERIOD (CLK_PERIOD),
357 .DQS_IO_COL (DQS_IO_COL),
358 .DQ_IO_MS (DQ_IO_MS),
367 .ddr2_ras_n (ddr2_ras_n),
368 .ddr2_cas_n (ddr2_cas_n),
369 .ddr2_we_n (ddr2_we_n),
370 .ddr2_cs_n (ddr2_cs_n),
371 .ddr2_odt (ddr2_odt),
372 .ddr2_cke (ddr2_cke),
374 .phy_init_done (phy_init_done),
382 //added by xtan & gdgib
392 .app_wdf_afull (app_wdf_afull),
393 .app_af_afull (app_af_afull),
394 .rd_data_valid (rd_data_valid),
395 .rd_data_rden(rd_data_rden),
396 .app_wdf_wren (app_wdf_wren),
397 .app_af_wren (app_af_wren),
398 .app_af_addr (app_af_addr),
399 .app_af_cmd (app_af_cmd),
400 .rd_data_fifo_out (rd_data_fifo_out),
401 .app_wdf_data (app_wdf_data),
402 .app_wdf_mask_data (app_wdf_mask_data),
403 .ddr2_dqs (ddr2_dqs),
404 .ddr2_dqs_n (ddr2_dqs_n),
406 .rd_ecc_error (rd_ecc_error),
407 .ddr2_ck_n (ddr2_ck_n),
409 .dbg_calib_done (dbg_calib_done),
410 .dbg_calib_err (dbg_calib_err),
411 .dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
412 .dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
413 .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
414 .dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
415 .dbg_calib_rden_dly (dbg_calib_rden_dly),
416 .dbg_calib_gate_dly (dbg_calib_gate_dly),
417 .dbg_idel_up_all (dbg_idel_up_all),
418 .dbg_idel_down_all (dbg_idel_down_all),
419 .dbg_idel_up_dq (dbg_idel_up_dq),
420 .dbg_idel_down_dq (dbg_idel_down_dq),
421 .dbg_idel_up_dqs (dbg_idel_up_dqs),
422 .dbg_idel_down_dqs (dbg_idel_down_dqs),
423 .dbg_idel_up_gate (dbg_idel_up_gate),
424 .dbg_idel_down_gate (dbg_idel_down_gate),
425 .dbg_sel_idel_dq (dbg_sel_idel_dq),
426 .dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
427 .dbg_sel_idel_dqs (dbg_sel_idel_dqs),
428 .dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
429 .dbg_sel_idel_gate (dbg_sel_idel_gate),
430 .dbg_sel_all_idel_gate (dbg_sel_all_idel_gate)
434 //*****************************************************************
435 // Hooks to prevent sim/syn compilation errors (mainly for VHDL - but
436 // keep it also in Verilog version of code) w/ floating inputs if
438 //*****************************************************************
441 if (DEBUG_EN == 0) begin: gen_dbg_tie_off
442 assign dbg_idel_up_all = 'b0;
443 assign dbg_idel_down_all = 'b0;
444 assign dbg_idel_up_dq = 'b0;
445 assign dbg_idel_down_dq = 'b0;
446 assign dbg_idel_up_dqs = 'b0;
447 assign dbg_idel_down_dqs = 'b0;
448 assign dbg_idel_up_gate = 'b0;
449 assign dbg_idel_down_gate = 'b0;
450 assign dbg_sel_idel_dq = 'b0;
451 assign dbg_sel_all_idel_dq = 'b0;
452 assign dbg_sel_idel_dqs = 'b0;
453 assign dbg_sel_all_idel_dqs = 'b0;
454 assign dbg_sel_idel_gate = 'b0;
455 assign dbg_sel_all_idel_gate = 'b0;
456 end else begin: gen_dbg_enable
458 //*****************************************************************
459 // PHY Debug Port example - see MIG User's Guide, XAPP858 or
460 // Answer Record 29443
461 // This logic supports up to 32 DQ and 8 DQS I/O
463 // 1. PHY Debug Port demo connects to 4 VIO modules:
464 // - 3 VIO modules with only asynchronous inputs
465 // * Monitor IDELAY taps for DQ, DQS, DQS Gate
466 // * Calibration status
467 // - 1 VIO module with synchronous outputs
468 // * Allow dynamic adjustment o f IDELAY taps
469 // 2. User may need to modify this code to incorporate other
470 // chipscope-related modules in their larger design (e.g.
471 // if they have other ILA/VIO modules, they will need to
472 // for example instantiate a larger ICON module). In addition
473 // user may want to instantiate more VIO modules to control
474 // IDELAY for more DQ, DQS than is shown here
475 //*****************************************************************
479 .control0 (cs_control0),
480 .control1 (cs_control1),
481 .control2 (cs_control2),
482 .control3 (cs_control3)
485 //*****************************************************************
486 // VIO ASYNC input: Display current IDELAY setting for up to 32
487 // DQ taps (32x6) = 192
488 //*****************************************************************
490 vio_async_in192 u_vio0
492 .control (cs_control0),
496 //*****************************************************************
497 // VIO ASYNC input: Display current IDELAY setting for up to 8 DQS
498 // and DQS Gate taps (8x6x2) = 96
499 //*****************************************************************
501 vio_async_in96 u_vio1
503 .control (cs_control1),
507 //*****************************************************************
508 // VIO ASYNC input: Display other calibration results
509 //*****************************************************************
511 vio_async_in100 u_vio2
513 .control (cs_control2),
517 //*****************************************************************
518 // VIO SYNC output: Dynamically change IDELAY taps
519 //*****************************************************************
521 vio_sync_out32 u_vio3
523 .control (cs_control3),
528 //*****************************************************************
530 // NOTE: Not all VIO, ILA inputs/outputs may be used - these will
531 // be dependent on the user's particular bit width
532 //*****************************************************************
534 if (DQ_WIDTH <= 32) begin: gen_dq_le_32
535 assign vio0_in[(6*DQ_WIDTH)-1:0]
536 = dbg_calib_dq_tap_cnt[(6*DQ_WIDTH)-1:0];
537 end else begin: gen_dq_gt_32
538 assign vio0_in = dbg_calib_dq_tap_cnt[191:0];
541 if (DQS_WIDTH <= 8) begin: gen_dqs_le_8
542 assign vio1_in[(6*DQS_WIDTH)-1:0]
543 = dbg_calib_dqs_tap_cnt[(6*DQS_WIDTH)-1:0];
544 assign vio1_in[(12*DQS_WIDTH)-1:(6*DQS_WIDTH)]
545 = dbg_calib_gate_tap_cnt[(6*DQS_WIDTH)-1:0];
546 end else begin: gen_dqs_gt_32
547 assign vio1_in[47:0] = dbg_calib_dqs_tap_cnt[47:0];
548 assign vio1_in[95:48] = dbg_calib_gate_tap_cnt[47:0];
551 //dbg_calib_rd_data_sel
553 if (DQS_WIDTH <= 8) begin: gen_rdsel_le_8
554 assign vio2_in[(DQS_WIDTH)+7:8]
555 = dbg_calib_rd_data_sel[(DQS_WIDTH)-1:0];
556 end else begin: gen_rdsel_gt_32
558 = dbg_calib_rd_data_sel[7:0];
563 if (DQS_WIDTH <= 8) begin: gen_calrd_le_8
564 assign vio2_in[(5*DQS_WIDTH)+19:20]
565 = dbg_calib_rden_dly[(5*DQS_WIDTH)-1:0];
566 end else begin: gen_calrd_gt_32
567 assign vio2_in[59:20]
568 = dbg_calib_rden_dly[39:0];
573 if (DQS_WIDTH <= 8) begin: gen_calgt_le_8
574 assign vio2_in[(5*DQS_WIDTH)+59:60]
575 = dbg_calib_gate_dly[(5*DQS_WIDTH)-1:0];
576 end else begin: gen_calgt_gt_32
577 assign vio2_in[99:60]
578 = dbg_calib_gate_dly[39:0];
583 if (DQ_BITS <= 5) begin: gen_selid_le_5
584 assign dbg_sel_idel_dq[DQ_BITS-1:0]
585 = vio3_out[DQ_BITS+7:8];
586 end else begin: gen_selid_gt_32
587 assign dbg_sel_idel_dq[4:0]
593 if (DQS_BITS <= 3) begin: gen_seldqs_le_3
594 assign dbg_sel_idel_dqs[DQS_BITS:0]
595 = vio3_out[(DQS_BITS+16):16];
596 end else begin: gen_seldqs_gt_32
597 assign dbg_sel_idel_dqs[3:0]
603 if (DQS_BITS <= 3) begin: gen_gtdqs_le_3
604 assign dbg_sel_idel_gate[DQS_BITS:0]
605 = vio3_out[(DQS_BITS+21):21];
606 end else begin: gen_gtdqs_gt_32
607 assign dbg_sel_idel_gate[3:0]
612 assign vio2_in[3:0] = dbg_calib_done;
613 assign vio2_in[7:4] = dbg_calib_err;
615 assign dbg_idel_up_all = vio3_out[0];
616 assign dbg_idel_down_all = vio3_out[1];
617 assign dbg_idel_up_dq = vio3_out[2];
618 assign dbg_idel_down_dq = vio3_out[3];
619 assign dbg_idel_up_dqs = vio3_out[4];
620 assign dbg_idel_down_dqs = vio3_out[5];
621 assign dbg_idel_up_gate = vio3_out[6];
622 assign dbg_idel_down_gate = vio3_out[7];
623 assign dbg_sel_all_idel_dq = vio3_out[15];
624 assign dbg_sel_all_idel_dqs = vio3_out[20];
625 assign dbg_sel_all_idel_gate = vio3_out[25];