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46 // /___/ \ / Vendor: Xilinx
47 // \ \ \/ Version: 2.3
48 // \ \ Application: MIG
49 // / / Filename: ddr2_usr_wr.v
50 // /___/ /\ Date Last Modified: $Date: 2008/05/08 15:20:47 $
51 // \ \ / \ Date Created: Mon Aug 28 2006
55 //Design Name: DDR/DDR2
57 // This module instantiates the modules containing internal FIFOs
60 //*****************************************************************************
66 // Following parameters are for 72-bit RDIMM design (for ML561 Reference
67 // board design). Actual values may be different. Actual parameters values
68 // are passed from design top module ddr2_sdram module. Please refer to
69 // the ddr2_sdram module for actual values.
70 parameter BANK_WIDTH = 2,
71 parameter COL_WIDTH = 10,
72 parameter CS_BITS = 0,
73 parameter DQ_WIDTH = 72,
74 parameter APPDATA_WIDTH = 144,
75 parameter APPDATA_BURST_LEN = 2,
76 parameter APPDATA_BURST_BITS = 1,
77 parameter ECC_ENABLE = 0,
78 parameter ROW_WIDTH = 14
81 input clk0, //write buffer phy clock
84 // start of changes xtan & gdgib
85 input wb_clk, //write buffer user clock
86 input wb_rst, //write buffer user reset
88 // Write data FIFO interface
90 input [APPDATA_WIDTH-1:0] app_wdf_data,
91 input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
94 output [(2*DQ_WIDTH)-1:0] wdf_data,
95 output [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data,
100 // determine number of FIFO72's to use based on data width
101 // round up to next integer value when determining WDF_FIFO_NUM
102 localparam WDF_FIFO_NUM = (ECC_ENABLE) ? (APPDATA_WIDTH+63)/64 :
103 ((2*DQ_WIDTH)+63)/64;
104 // MASK_WIDTH = number of bytes in data bus
105 localparam MASK_WIDTH = DQ_WIDTH/8;
107 wire [WDF_FIFO_NUM-1:0] i_wdf_afull;
108 wire [DQ_WIDTH-1:0] i_wdf_data_fall_in;
109 wire [DQ_WIDTH-1:0] i_wdf_data_fall_out;
110 wire [(64*WDF_FIFO_NUM)-1:0] i_wdf_data_in;
111 wire [(64*WDF_FIFO_NUM)-1:0] i_wdf_data_out;
112 wire [DQ_WIDTH-1:0] i_wdf_data_rise_in;
113 wire [DQ_WIDTH-1:0] i_wdf_data_rise_out;
114 wire [MASK_WIDTH-1:0] i_wdf_mask_data_fall_in;
115 wire [MASK_WIDTH-1:0] i_wdf_mask_data_fall_out;
116 wire [(8*WDF_FIFO_NUM)-1:0] i_wdf_mask_data_in;
117 wire [(8*WDF_FIFO_NUM)-1:0] i_wdf_mask_data_out;
118 wire [MASK_WIDTH-1:0] i_wdf_mask_data_rise_in;
119 wire [MASK_WIDTH-1:0] i_wdf_mask_data_rise_out;
123 wire [(2*DQ_WIDTH)-1:0] i_wdf_data_out_ecc;
124 wire [((2*DQ_WIDTH)/8)-1:0] i_wdf_mask_data_out_ecc;
125 wire [63:0] i_wdf_mask_data_out_ecc_wire;
126 wire [((2*DQ_WIDTH)/8)-1:0] mask_data_in_ecc;
127 wire [63:0] mask_data_in_ecc_wire;
129 //***************************************************************************
131 reg [APPDATA_BURST_BITS-1:0] blfifo_writecount;
132 wire blfifo_writeterminal;
134 wire blfifo_empty, blfifo_full;
136 // Doesn't NEED to be async for now, but will need to be if we add async data writes....
137 asyncfifo_dmem_1b blfifo (
140 .rd_en(wr_fifo_burst),
141 .rst(rst_r | wb_rst),
143 .wr_en(blfifo_write),
145 .empty(blfifo_empty),
147 assign wr_fifo_clear = ~blfifo_empty;
149 always @ (posedge wb_clk) begin
150 if (wb_rst) blfifo_writecount <= 0;
151 else if (app_wdf_wren & ~blfifo_full) begin
152 if (blfifo_writeterminal) blfifo_writecount <= 0;
153 else blfifo_writecount <= blfifo_writecount + 1;
157 assign blfifo_writeterminal = (blfifo_writecount == (APPDATA_BURST_LEN - 1));
158 assign blfifo_write = blfifo_writeterminal & app_wdf_wren & ~blfifo_full;
160 //***************************************************************************
162 assign app_wdf_afull = i_wdf_afull[0] | blfifo_full;
164 always @(posedge clk0 )
172 if(ECC_ENABLE) begin // ECC code
174 assign wdf_data = i_wdf_data_out_ecc;
176 // the byte 9 dm is always held to 0
177 assign wdf_mask_data = i_wdf_mask_data_out_ecc;
181 // generate for write data fifo .
182 for (wdf_i = 0; wdf_i < WDF_FIFO_NUM; wdf_i = wdf_i + 1) begin: gen_wdf
186 .ALMOST_EMPTY_OFFSET (9'h007),
187 .ALMOST_FULL_OFFSET (9'h00F),
188 .DO_REG (1), // extra CC output delay
189 .EN_ECC_WRITE ("TRUE"),
190 .EN_ECC_READ ("FALSE"),
192 .FIRST_WORD_FALL_THROUGH ("FALSE")
197 .ALMOSTFULL (i_wdf_afull[wdf_i]),
199 .DO (i_wdf_data_out_ecc[((64*(wdf_i+1))+(wdf_i *8))-1:
200 (64*wdf_i)+(wdf_i *8)]),
201 .DOP (i_wdf_data_out_ecc[(72*(wdf_i+1))-1:
202 (64*(wdf_i+1))+ (8*wdf_i) ]),
211 .DI (app_wdf_data[(64*(wdf_i+1))-1:
216 .RST (rst_r | wb_rst), // or can use rst0
217 .WRCLK (wb_clk), // xtan: clk0 -> wb_clk
218 .WREN (app_wdf_wren & ~blfifo_full)
222 // remapping the mask data. The mask data from user i/f does not have
223 // the mask for the ECC byte. Assigning 0 to the ECC mask byte.
224 for (mask_i = 0; mask_i < (DQ_WIDTH)/36;
225 mask_i = mask_i +1) begin: gen_mask
226 assign mask_data_in_ecc[((8*(mask_i+1))+ mask_i)-1:((8*mask_i)+mask_i)]
227 = app_wdf_mask_data[(8*(mask_i+1))-1:8*(mask_i)] ;
228 assign mask_data_in_ecc[((8*(mask_i+1))+mask_i)] = 1'd0;
231 // assign ecc bits to temp variables to avoid
232 // sim warnings. Not all the 64 bits of the fifo
233 // are used in ECC mode.
234 assign mask_data_in_ecc_wire[((2*DQ_WIDTH)/8)-1:0] = mask_data_in_ecc;
235 assign mask_data_in_ecc_wire[63:((2*DQ_WIDTH)/8)] =
236 {(64-((2*DQ_WIDTH)/8)){1'b0}};
237 assign i_wdf_mask_data_out_ecc =
238 i_wdf_mask_data_out_ecc_wire[((2*DQ_WIDTH)/8)-1:0];
243 .ALMOST_EMPTY_OFFSET (9'h007),
244 .ALMOST_FULL_OFFSET (9'h00F),
245 .DO_REG (1), // extra CC output delay
246 .EN_ECC_WRITE ("TRUE"),
247 .EN_ECC_READ ("FALSE"),
249 .FIRST_WORD_FALL_THROUGH ("FALSE")
256 .DO (i_wdf_mask_data_out_ecc_wire),
266 .DI (mask_data_in_ecc_wire),
270 .RST (rst_r | wb_rst), // or can use rst0
271 .WRCLK (wb_clk), // xtan: clk0->wb_clk
272 .WREN (app_wdf_wren & ~blfifo_full)
276 //***********************************************************************
278 // Define intermediate buses:
279 assign i_wdf_data_rise_in
280 = app_wdf_data[DQ_WIDTH-1:0];
281 assign i_wdf_data_fall_in
282 = app_wdf_data[(2*DQ_WIDTH)-1:DQ_WIDTH];
283 assign i_wdf_mask_data_rise_in
284 = app_wdf_mask_data[MASK_WIDTH-1:0];
285 assign i_wdf_mask_data_fall_in
286 = app_wdf_mask_data[(2*MASK_WIDTH)-1:MASK_WIDTH];
288 //***********************************************************************
289 // Write data FIFO Input:
290 // Arrange DQ's so that the rise data and fall data are interleaved.
291 // the data arrives at the input of the wdf fifo as {fall,rise}.
292 // It is remapped as:
293 // {...fall[15:8],rise[15:8],fall[7:0],rise[7:0]}
294 // This is done to avoid having separate fifo's for rise and fall data
295 // and to keep rise/fall data for the same DQ's on same FIFO
296 // Data masks are interleaved in a similar manner
297 // NOTE: Initialization data from PHY_INIT module does not need to be
298 // interleaved - it's already in the correct format - and the same
299 // initialization pattern from PHY_INIT is sent to all write FIFOs
300 //***********************************************************************
302 for (wdf_di_i = 0; wdf_di_i < MASK_WIDTH;
303 wdf_di_i = wdf_di_i + 1) begin: gen_wdf_data_in
304 assign i_wdf_data_in[(16*wdf_di_i)+15:(16*wdf_di_i)]
305 = {i_wdf_data_fall_in[(8*wdf_di_i)+7:(8*wdf_di_i)],
306 i_wdf_data_rise_in[(8*wdf_di_i)+7:(8*wdf_di_i)]};
307 assign i_wdf_mask_data_in[(2*wdf_di_i)+1:(2*wdf_di_i)]
308 = {i_wdf_mask_data_fall_in[wdf_di_i],
309 i_wdf_mask_data_rise_in[wdf_di_i]};
312 //***********************************************************************
313 // Write data FIFO Output:
314 // FIFO DQ and mask outputs must be untangled and put in the standard
315 // format of {fall,rise}. Same goes for mask output
316 //***********************************************************************
318 for (wdf_do_i = 0; wdf_do_i < MASK_WIDTH;
319 wdf_do_i = wdf_do_i + 1) begin: gen_wdf_data_out
320 assign i_wdf_data_rise_out[(8*wdf_do_i)+7:(8*wdf_do_i)]
321 = i_wdf_data_out[(16*wdf_do_i)+7:(16*wdf_do_i)];
322 assign i_wdf_data_fall_out[(8*wdf_do_i)+7:(8*wdf_do_i)]
323 = i_wdf_data_out[(16*wdf_do_i)+15:(16*wdf_do_i)+8];
324 assign i_wdf_mask_data_rise_out[wdf_do_i]
325 = i_wdf_mask_data_out[2*wdf_do_i];
326 assign i_wdf_mask_data_fall_out[wdf_do_i]
327 = i_wdf_mask_data_out[(2*wdf_do_i)+1];
330 assign wdf_data = {i_wdf_data_fall_out,
331 i_wdf_data_rise_out};
333 assign wdf_mask_data = {i_wdf_mask_data_fall_out,
334 i_wdf_mask_data_rise_out};
336 //***********************************************************************
338 for (wdf_i = 0; wdf_i < WDF_FIFO_NUM; wdf_i = wdf_i + 1) begin: gen_wdf
342 .ALMOST_EMPTY_OFFSET (9'h007),
343 .ALMOST_FULL_OFFSET (9'h00F),
344 .DO_REG (1), // extra CC output delay
345 .EN_ECC_WRITE ("FALSE"),
346 .EN_ECC_READ ("FALSE"),
348 .FIRST_WORD_FALL_THROUGH ("FALSE")
353 .ALMOSTFULL (i_wdf_afull[wdf_i]),
355 .DO (i_wdf_data_out[(64*(wdf_i+1))-1:64*wdf_i]),
356 .DOP (i_wdf_mask_data_out[(8*(wdf_i+1))-1:8*wdf_i]),
365 .DI (i_wdf_data_in[(64*(wdf_i+1))-1:64*wdf_i]),
366 .DIP (i_wdf_mask_data_in[(8*(wdf_i+1))-1:8*wdf_i]),
369 .RST (rst_r | wb_rst), // or can use rst0
370 .WRCLK (wb_clk), // xtan: clk0 -> wb_clk
371 .WREN (app_wdf_wren & ~blfifo_full)