src/edu/berkeley/fleet/fpga/main.ucf

   1 ############################################################################
   2 ## This system.ucf file is generated by Base System Builder based on the
   3 ## settings in the selected Xilinx Board Definition file. Please add other
   4 ## user constraints to this file based on customer design specifications.
   5 ############################################################################
   6
   7 #Net fpga_0_PCI32_BRIDGE_PCI_INTA LOC=P5;
   8 #Net fpga_0_PCI32_BRIDGE_PCI_INTA IOSTANDARD = PCI33_3;
   9 #Net fpga_0_PCI32_BRIDGE_PCI_INTA TIG;
  10 #Net fpga_0_PCI32_BRIDGE_PCI_INTB LOC=R8;
  11 #Net fpga_0_PCI32_BRIDGE_PCI_INTB IOSTANDARD = PCI33_3;
  12 #Net fpga_0_PCI32_BRIDGE_PCI_INTB TIG;
  13 #Net fpga_0_PCI32_BRIDGE_PCI_INTC LOC=P9;
  14 #Net fpga_0_PCI32_BRIDGE_PCI_INTC IOSTANDARD = PCI33_3;
  15 #Net fpga_0_PCI32_BRIDGE_PCI_INTC TIG;
  16 #Net fpga_0_PCI32_BRIDGE_PCI_INTD LOC=V4;
  17 #Net fpga_0_PCI32_BRIDGE_PCI_INTD IOSTANDARD = PCI33_3;
  18 #Net fpga_0_PCI32_BRIDGE_PCI_INTD TIG;
  19 #Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT LOC=AE21;
  20 #Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT IOSTANDARD = LVCMOS25;
  21 #Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT TIG;
  22 Net sys_clk_pin LOC=J16;
  23 Net sys_clk_pin IOSTANDARD = LVCMOS25;
  24 Net sys_rst_pin LOC=H7;
  25 Net sys_rst_pin PULLUP;
  26 Net sys_rst_pin IOSTANDARD = LVCMOS33;
  27
  28 ### System level constraints
  29
  30 Net sys_clk_pin TNM_NET = sys_clk_pin;
  31 TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10 ns HIGH 50%;
  32
  33 Net clk_unbuffered TNM_NET = clk_unbuffered;
  34 TIMESPEC TS_clk_unbuffered = PERIOD clk_unbuffered 20 ns;
  35
  36 Net vga_clk_unbuffered TNM_NET = vga_clk_unbuffered;
  37 TIMESPEC TS_vga_clk_unbuffered = PERIOD vga_clk_unbuffered 40 ns;
  38
  39 Net sys_rst_pin TIG;
  40
  41 NET "sys_clk_pin"               TNM="SYS_CLK";
  42 NET "*/clkgen/write_clk_u"    TNM="WRITE_CLK";
  43 NET "*/clkgen/write_clk90_u"  TNM="WRITE_CLK";
  44 NET "*/clkgen/read_clk_u"     TNM="READ_CLK";
  45 TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG;
  46 TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG;
  47 TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG;
  48 TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG;
  49 TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG;
  50 TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG;
  51
  52 net "vga_hsync" loc   = f9;
  53 net "vga_hsync" slew  = slow;
  54 net "vga_hsync" drive = 2;
  55
  56 net "vga_vsync" loc   = h10;
  57 net "vga_vsync" slew  = slow;
  58 net "vga_vsync" drive = 2;
  59
  60 net "vga_clkout"  loc ="c12";
  61 net "vga_clkout"  slew = fast;
  62 net "vga_clkout"  drive = 8;
  63
  64 net "vga_r<7>" loc ="h8";
  65 net "vga_r<6>" loc ="c5";
  66 net "vga_r<5>" loc ="h9";
  67 net "vga_r<4>" loc ="g12";
  68 net "vga_r<3>" loc ="g11";
  69 net "vga_r<2>" loc ="g10";
  70 net "vga_r<1>" loc ="f11";
  71 net "vga_r<0>" loc ="f10";
  72 net "vga_r<*>" slew = slow;
  73 net "vga_r<*>" drive = 2;
  74
  75 net "vga_g<7>" loc ="d5";
  76 net "vga_g<6>" loc ="d4";
  77 net "vga_g<5>" loc ="f8";
  78 net "vga_g<4>" loc ="e13";
  79 net "vga_g<3>" loc ="e12";
  80 net "vga_g<2>" loc ="e11";
  81 net "vga_g<1>" loc ="e9";
  82 net "vga_g<0>" loc ="e8";
  83 net "vga_g<*>" slew = slow;
  84 net "vga_g<*>" drive = 2;
  85
  86 net "vga_b<7>" loc ="c4";
  87 net "vga_b<6>" loc ="c3";
  88 net "vga_b<5>" loc ="d12";
  89 net "vga_b<4>" loc ="d11";
  90 net "vga_b<3>" loc ="d10";
  91 net "vga_b<2>" loc ="d9";
  92 net "vga_b<1>" loc ="c13";
  93 net "vga_b<0>" loc ="g8";
  94 net "vga_b<*>" slew = slow;
  95 net "vga_b<*>" drive = 2;
  96
  97 net "vga_*" iostandard = lvcmos33;
  98
  99
 100 #NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
 101 #NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
 102 #NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
 103 #TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;
 104 #Net fpga_0_PCI_CLK_FB LOC=H17;
 105 #Net fpga_0_PCI_CLK_FB IOSTANDARD = LVCMOS25;
 106 #Net fpga_0_PCI_CLK_FB TNM_NET = PCI_CLK;
 107 #Net PCI32_BRIDGE/OPB_Clk TNM_NET = SYS_CLK;
 108 ##TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 10000 ps;
 109 #TIMESPEC "TS_PCI_BUS" = FROM "PCI_CLK" TO "SYS_CLK" 9.9ns datapathonly;
 110 #TIMESPEC TS_BUS_PCI = FROM SYS_CLK TO PCI_CLK 30000 ps;
 111 #Net fpga_0_PCI_CLK_OUT0 LOC=V5;
 112 #Net fpga_0_PCI_CLK_OUT0 IOSTANDARD = PCI33_3;
 113 #Net fpga_0_PCI_CLK_OUT1 LOC=T11;
 114 #Net fpga_0_PCI_CLK_OUT1 IOSTANDARD = PCI33_3;
 115 #Net fpga_0_PCI_CLK_OUT2 LOC=U6;
 116 #Net fpga_0_PCI_CLK_OUT2 IOSTANDARD = PCI33_3;
 117 #Net fpga_0_PCI_CLK_OUT3 LOC=U7;
 118 #Net fpga_0_PCI_CLK_OUT3 IOSTANDARD = PCI33_3;
 119 #Net fpga_0_PCI_CLK_OUT4 LOC=U3;
 120 #Net fpga_0_PCI_CLK_OUT4 IOSTANDARD = PCI33_3;
 121 #Net fpga_0_PCI_CLK_OUT5 LOC=U5;
 122 #Net fpga_0_PCI_CLK_OUT5 IOSTANDARD = PCI33_3;
 123 #Net fpga_0_DDR_CLK_FB LOC=K18;
 124 #Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS25;
 125 #
 126 ### IO Devices constraints
 127 #
 128 ##### Module RS232_Uart_1 constraints
 129 #
 130 Net fpga_0_RS232_Uart_1_ctsN_pin LOC=G6;
 131 Net fpga_0_RS232_Uart_1_ctsN_pin IOSTANDARD = LVCMOS33;
 132 Net fpga_0_RS232_Uart_1_ctsN_pin TIG;
 133 Net fpga_0_RS232_Uart_1_rtsN_pin LOC=F6;
 134 Net fpga_0_RS232_Uart_1_rtsN_pin IOSTANDARD = LVCMOS33;
 135 Net fpga_0_RS232_Uart_1_rtsN_pin TIG;
 136
 137 Net fpga_0_RS232_Uart_1_sin_pin LOC=E6;
 138 Net fpga_0_RS232_Uart_1_sin_pin IOSTANDARD = LVCMOS33;
 139 Net fpga_0_RS232_Uart_1_sin_pin TIG;
 140 Net fpga_0_RS232_Uart_1_sin_pin PULLUP;
 141
 142 Net fpga_0_RS232_Uart_1_sout_pin LOC=D6;
 143 Net fpga_0_RS232_Uart_1_sout_pin IOSTANDARD = LVCMOS33;
 144 Net fpga_0_RS232_Uart_1_sout_pin TIG;
 145 Net fpga_0_RS232_Uart_1_sout_pin PULLUP;
 146
 147 ##### Module DDR_SDRAM_32Mx64 constraints
 148 #
 149 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> LOC=P24;
 150 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
 151 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> LOC=P22;
 152 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
 153 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> LOC=N22;
 154 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
 155 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> LOC=N23;
 156 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
 157 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> LOC=N24;
 158 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
 159 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> LOC=M23;
 160 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
 161 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> LOC=L24;
 162 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
 163 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> LOC=L25;
 164 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
 165 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> LOC=L26;
 166 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
 167 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> LOC=K23;
 168 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
 169 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> LOC=K24;
 170 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
 171 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> LOC=K26;
 172 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
 173 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> LOC=J24;
 174 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
 175 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> LOC=J25;
 176 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
 177 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> LOC=J26;
 178 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
 179 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin LOC=D26;
 180 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin IOSTANDARD = SSTL2_I;
 181 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin LOC=H14;
 182 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin IOSTANDARD = SSTL2_I;
 183 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin LOC=C27;
 184 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin IOSTANDARD = SSTL2_I;
 185 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin LOC=D27;
 186 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin IOSTANDARD = SSTL2_I;
 187 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin LOC=E27;
 188 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin IOSTANDARD = SSTL2_I;
 189 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> LOC=G23;
 190 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
 191 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> LOC=E23;
 192 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
 193 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> LOC=G22;
 194 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
 195 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> LOC=F21;
 196 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
 197 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> LOC=F25;
 198 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
 199 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> LOC=G25;
 200 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
 201 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> LOC=G20;
 202 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
 203 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> LOC=F20;
 204 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
 205 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> LOC=E22;
 206 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
 207 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> LOC=E24;
 208 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
 209 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> LOC=H24;
 210 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
 211 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> LOC=H25;
 212 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
 213 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> LOC=G26;
 214 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
 215 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> LOC=F26;
 216 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
 217 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> LOC=F24;
 218 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
 219 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> LOC=F23;
 220 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
 221 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> LOC=C28;
 222 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
 223 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> LOC=D25;
 224 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
 225 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> LOC=D24;
 226 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
 227 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> LOC=D22;
 228 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
 229 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> LOC=C25;
 230 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
 231 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> LOC=C24;
 232 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
 233 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> LOC=C23;
 234 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
 235 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> LOC=C22;
 236 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
 237 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> LOC=H22;
 238 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
 239 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> LOC=J22;
 240 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
 241 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> LOC=L21;
 242 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
 243 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> LOC=K21;
 244 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
 245 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> LOC=J21;
 246 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
 247 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> LOC=J20;
 248 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
 249 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> LOC=H20;
 250 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
 251 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> LOC=G21;
 252 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
 253 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> LOC=E21;
 254 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
 255 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> LOC=D21;
 256 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
 257 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> LOC=E19;
 258 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
 259 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> LOC=F19;
 260 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
 261 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> LOC=G18;
 262 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
 263 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> LOC=F18;
 264 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
 265 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> LOC=E18;
 266 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
 267 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> LOC=E17;
 268 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
 269 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin LOC=F28;
 270 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin IOSTANDARD = SSTL2_I;
 271 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin LOC=E28;
 272 #Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin IOSTANDARD = SSTL2_I;
 273 #
 274 ##### Module SPI_EEPROM constraints
 275 #
 276 #Net fpga_0_SPI_EEPROM_SCK_pin LOC=AF21;
 277 #Net fpga_0_SPI_EEPROM_SCK_pin IOSTANDARD = LVCMOS25;
 278 #Net fpga_0_SPI_EEPROM_SCK_pin TIG;
 279 #Net fpga_0_SPI_EEPROM_SCK_pin PULLUP;
 280 #Net fpga_0_SPI_EEPROM_MOSI_pin LOC=AH22;
 281 #Net fpga_0_SPI_EEPROM_MOSI_pin TIG;
 282 #Net fpga_0_SPI_EEPROM_MOSI_pin PULLUP;
 283 #Net fpga_0_SPI_EEPROM_MISO_pin LOC=AJ22;
 284 #Net fpga_0_SPI_EEPROM_MISO_pin TIG;
 285 #Net fpga_0_SPI_EEPROM_MISO_pin PULLUP;
 286 #Net fpga_0_SPI_EEPROM_SS_pin<0> LOC=AG22;
 287 #Net fpga_0_SPI_EEPROM_SS_pin<0> TIG;
 288 #Net fpga_0_SPI_EEPROM_SS_pin<0> PULLUP;
 289 #
 290 ##### Module LEDs_8Bit constraints
 291 #
 292 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC=AF19;
 293 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
 294 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> TIG;
 295 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC=AD5;
 296 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33;
 297 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> TIG;
 298 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC=AD6;
 299 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33;
 300 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> TIG;
 301 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC=AD7;
 302 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33;
 303 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> TIG;
 304 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC=AB8;
 305 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33;
 306 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> TIG;
 307 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC=AC7;
 308 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33;
 309 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> TIG;
 310 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC=AC9;
 311 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33;
 312 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> TIG;
 313 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC=AC10;
 314 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS33;
 315 Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> TIG;
 316 #
 317 ##### Module LCD_OPTIONAL constraints
 318 #
 319 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> LOC=AH19;
 320 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
 321 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> TIG;
 322 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> LOC=AJ19;
 323 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
 324 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> TIG;
 325 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> LOC=AK19;
 326 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
 327 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> TIG;
 328 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> LOC=AG20;
 329 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
 330 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> TIG;
 331 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> LOC=AH20;
 332 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
 333 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> TIG;
 334 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> LOC=AJ20;
 335 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25;
 336 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> TIG;
 337 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> LOC=AG21;
 338 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25;
 339 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> TIG;
 340 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> LOC=AJ21;
 341 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25;
 342 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> TIG;
 343 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> LOC=AK17;
 344 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> IOSTANDARD = LVCMOS25;
 345 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> TIG;
 346 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> LOC=AH18;
 347 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> IOSTANDARD = LVCMOS25;
 348 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> TIG;
 349 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> LOC=AK18;
 350 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> IOSTANDARD = LVCMOS25;
 351 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> TIG;
 352 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> LOC=AJ17;
 353 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> IOSTANDARD = LVCMOS25;
 354 #Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> TIG;
 355 #
 356 ##### Module pci_arbiter_0 constraints
 357 #
 358 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> LOC=T4;
 359 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> IOSTANDARD = PCI33_3;
 360 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> LOC=T5;
 361 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> IOSTANDARD = PCI33_3;
 362 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> LOC=U8;
 363 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> IOSTANDARD = PCI33_3;
 364 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> LOC=V3;
 365 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> IOSTANDARD = PCI33_3;
 366 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> LOC=T6;
 367 #Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> IOSTANDARD = PCI33_3;
 368 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> LOC=T3;
 369 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> IOSTANDARD = PCI33_3;
 370 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> LOC=R7;
 371 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> IOSTANDARD = PCI33_3;
 372 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> LOC=T8;
 373 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> IOSTANDARD = PCI33_3;
 374 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> LOC=T9;
 375 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> IOSTANDARD = PCI33_3;
 376 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> LOC=R9;
 377 #Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> IOSTANDARD = PCI33_3;
 378 #
 379 ##### Module PCI32_BRIDGE constraints
 380 #
 381 #Net fpga_0_PCI32_BRIDGE_PAR LOC=L8;
 382 #Net fpga_0_PCI32_BRIDGE_PAR IOSTANDARD = PCI33_3;
 383 #Net fpga_0_PCI32_BRIDGE_PAR BYPASS;
 384 #Net fpga_0_PCI32_BRIDGE_PERR_N LOC=M6;
 385 #Net fpga_0_PCI32_BRIDGE_PERR_N IOSTANDARD = PCI33_3;
 386 #Net fpga_0_PCI32_BRIDGE_PERR_N BYPASS;
 387 #Net fpga_0_PCI32_BRIDGE_SERR_N LOC=M7;
 388 #Net fpga_0_PCI32_BRIDGE_SERR_N IOSTANDARD = PCI33_3;
 389 #Net fpga_0_PCI32_BRIDGE_SERR_N BYPASS;
 390 #Net fpga_0_PCI32_BRIDGE_IRDY_N LOC=N5;
 391 #Net fpga_0_PCI32_BRIDGE_IRDY_N IOSTANDARD = PCI33_3;
 392 #Net fpga_0_PCI32_BRIDGE_IRDY_N BYPASS;
 393 #Net fpga_0_PCI32_BRIDGE_FRAME_N LOC=N8;
 394 #Net fpga_0_PCI32_BRIDGE_FRAME_N IOSTANDARD = PCI33_3;
 395 #Net fpga_0_PCI32_BRIDGE_FRAME_N BYPASS;
 396 #Net fpga_0_PCI32_BRIDGE_DEVSEL_N LOC=R3;
 397 #Net fpga_0_PCI32_BRIDGE_DEVSEL_N IOSTANDARD = PCI33_3;
 398 #Net fpga_0_PCI32_BRIDGE_DEVSEL_N BYPASS;
 399 #Net fpga_0_PCI32_BRIDGE_STOP_N LOC=P11;
 400 #Net fpga_0_PCI32_BRIDGE_STOP_N IOSTANDARD = PCI33_3;
 401 #Net fpga_0_PCI32_BRIDGE_STOP_N BYPASS;
 402 #Net fpga_0_PCI32_BRIDGE_TRDY_N LOC=M3;
 403 #Net fpga_0_PCI32_BRIDGE_TRDY_N IOSTANDARD = PCI33_3;
 404 #Net fpga_0_PCI32_BRIDGE_TRDY_N BYPASS;
 405 #Net fpga_0_PCI32_BRIDGE_AD<31> LOC=P7;
 406 #Net fpga_0_PCI32_BRIDGE_AD<31> IOSTANDARD = PCI33_3;
 407 #Net fpga_0_PCI32_BRIDGE_AD<31> BYPASS;
 408 #Net fpga_0_PCI32_BRIDGE_AD<30> LOC=P6;
 409 #Net fpga_0_PCI32_BRIDGE_AD<30> IOSTANDARD = PCI33_3;
 410 #Net fpga_0_PCI32_BRIDGE_AD<30> BYPASS;
 411 #Net fpga_0_PCI32_BRIDGE_AD<29> LOC=K7;
 412 #Net fpga_0_PCI32_BRIDGE_AD<29> IOSTANDARD = PCI33_3;
 413 #Net fpga_0_PCI32_BRIDGE_AD<29> BYPASS;
 414 #Net fpga_0_PCI32_BRIDGE_AD<28> LOC=K6;
 415 #Net fpga_0_PCI32_BRIDGE_AD<28> IOSTANDARD = PCI33_3;
 416 #Net fpga_0_PCI32_BRIDGE_AD<28> BYPASS;
 417 #Net fpga_0_PCI32_BRIDGE_AD<27> LOC=L3;
 418 #Net fpga_0_PCI32_BRIDGE_AD<27> IOSTANDARD = PCI33_3;
 419 #Net fpga_0_PCI32_BRIDGE_AD<27> BYPASS;
 420 #Net fpga_0_PCI32_BRIDGE_AD<26> LOC=K8;
 421 #Net fpga_0_PCI32_BRIDGE_AD<26> IOSTANDARD = PCI33_3;
 422 #Net fpga_0_PCI32_BRIDGE_AD<26> BYPASS;
 423 #Net fpga_0_PCI32_BRIDGE_AD<25> LOC=M10;
 424 #Net fpga_0_PCI32_BRIDGE_AD<25> IOSTANDARD = PCI33_3;
 425 #Net fpga_0_PCI32_BRIDGE_AD<25> BYPASS;
 426 #Net fpga_0_PCI32_BRIDGE_AD<24> LOC=M8;
 427 #Net fpga_0_PCI32_BRIDGE_AD<24> IOSTANDARD = PCI33_3;
 428 #Net fpga_0_PCI32_BRIDGE_AD<24> BYPASS;
 429 #Net fpga_0_PCI32_BRIDGE_AD<23> LOC=J7;
 430 #Net fpga_0_PCI32_BRIDGE_AD<23> IOSTANDARD = PCI33_3;
 431 #Net fpga_0_PCI32_BRIDGE_AD<23> BYPASS;
 432 #Net fpga_0_PCI32_BRIDGE_AD<22> LOC=J6;
 433 #Net fpga_0_PCI32_BRIDGE_AD<22> IOSTANDARD = PCI33_3;
 434 #Net fpga_0_PCI32_BRIDGE_AD<22> BYPASS;
 435 #Net fpga_0_PCI32_BRIDGE_AD<21> LOC=K4;
 436 #Net fpga_0_PCI32_BRIDGE_AD<21> IOSTANDARD = PCI33_3;
 437 #Net fpga_0_PCI32_BRIDGE_AD<21> BYPASS;
 438 #Net fpga_0_PCI32_BRIDGE_AD<20> LOC=K3;
 439 #Net fpga_0_PCI32_BRIDGE_AD<20> IOSTANDARD = PCI33_3;
 440 #Net fpga_0_PCI32_BRIDGE_AD<20> BYPASS;
 441 #Net fpga_0_PCI32_BRIDGE_AD<19> LOC=N10;
 442 #Net fpga_0_PCI32_BRIDGE_AD<19> IOSTANDARD = PCI33_3;
 443 #Net fpga_0_PCI32_BRIDGE_AD<19> BYPASS;
 444 #Net fpga_0_PCI32_BRIDGE_AD<18> LOC=N9;
 445 #Net fpga_0_PCI32_BRIDGE_AD<18> IOSTANDARD = PCI33_3;
 446 #Net fpga_0_PCI32_BRIDGE_AD<18> BYPASS;
 447 #Net fpga_0_PCI32_BRIDGE_AD<17> LOC=H5;
 448 #Net fpga_0_PCI32_BRIDGE_AD<17> IOSTANDARD = PCI33_3;
 449 #Net fpga_0_PCI32_BRIDGE_AD<17> BYPASS;
 450 #Net fpga_0_PCI32_BRIDGE_AD<16> LOC=H4;
 451 #Net fpga_0_PCI32_BRIDGE_AD<16> IOSTANDARD = PCI33_3;
 452 #Net fpga_0_PCI32_BRIDGE_AD<16> BYPASS;
 453 #Net fpga_0_PCI32_BRIDGE_AD<15> LOC=J5;
 454 #Net fpga_0_PCI32_BRIDGE_AD<15> IOSTANDARD = PCI33_3;
 455 #Net fpga_0_PCI32_BRIDGE_AD<15> BYPASS;
 456 #Net fpga_0_PCI32_BRIDGE_AD<14> LOC=J4;
 457 #Net fpga_0_PCI32_BRIDGE_AD<14> IOSTANDARD = PCI33_3;
 458 #Net fpga_0_PCI32_BRIDGE_AD<14> BYPASS;
 459 #Net fpga_0_PCI32_BRIDGE_AD<13> LOC=L10;
 460 #Net fpga_0_PCI32_BRIDGE_AD<13> IOSTANDARD = PCI33_3;
 461 #Net fpga_0_PCI32_BRIDGE_AD<13> BYPASS;
 462 #Net fpga_0_PCI32_BRIDGE_AD<12> LOC=L9;
 463 #Net fpga_0_PCI32_BRIDGE_AD<12> IOSTANDARD = PCI33_3;
 464 #Net fpga_0_PCI32_BRIDGE_AD<12> BYPASS;
 465 #Net fpga_0_PCI32_BRIDGE_AD<11> LOC=G3;
 466 #Net fpga_0_PCI32_BRIDGE_AD<11> IOSTANDARD = PCI33_3;
 467 #Net fpga_0_PCI32_BRIDGE_AD<11> BYPASS;
 468 #Net fpga_0_PCI32_BRIDGE_AD<10> LOC=F5;
 469 #Net fpga_0_PCI32_BRIDGE_AD<10> IOSTANDARD = PCI33_3;
 470 #Net fpga_0_PCI32_BRIDGE_AD<10> BYPASS;
 471 #Net fpga_0_PCI32_BRIDGE_AD<9> LOC=F3;
 472 #Net fpga_0_PCI32_BRIDGE_AD<9> IOSTANDARD = PCI33_3;
 473 #Net fpga_0_PCI32_BRIDGE_AD<9> BYPASS;
 474 #Net fpga_0_PCI32_BRIDGE_AD<8> LOC=G5;
 475 #Net fpga_0_PCI32_BRIDGE_AD<8> IOSTANDARD = PCI33_3;
 476 #Net fpga_0_PCI32_BRIDGE_AD<8> BYPASS;
 477 #Net fpga_0_PCI32_BRIDGE_AD<7> LOC=N4;
 478 #Net fpga_0_PCI32_BRIDGE_AD<7> IOSTANDARD = PCI33_3;
 479 #Net fpga_0_PCI32_BRIDGE_AD<7> BYPASS;
 480 #Net fpga_0_PCI32_BRIDGE_AD<6> LOC=N3;
 481 #Net fpga_0_PCI32_BRIDGE_AD<6> IOSTANDARD = PCI33_3;
 482 #Net fpga_0_PCI32_BRIDGE_AD<6> BYPASS;
 483 #Net fpga_0_PCI32_BRIDGE_AD<5> LOC=E4;
 484 #Net fpga_0_PCI32_BRIDGE_AD<5> IOSTANDARD = PCI33_3;
 485 #Net fpga_0_PCI32_BRIDGE_AD<5> BYPASS;
 486 #Net fpga_0_PCI32_BRIDGE_AD<4> LOC=E3;
 487 #Net fpga_0_PCI32_BRIDGE_AD<4> IOSTANDARD = PCI33_3;
 488 #Net fpga_0_PCI32_BRIDGE_AD<4> BYPASS;
 489 #Net fpga_0_PCI32_BRIDGE_AD<3> LOC=F4;
 490 #Net fpga_0_PCI32_BRIDGE_AD<3> IOSTANDARD = PCI33_3;
 491 #Net fpga_0_PCI32_BRIDGE_AD<3> BYPASS;
 492 #Net fpga_0_PCI32_BRIDGE_AD<2> LOC=H3;
 493 #Net fpga_0_PCI32_BRIDGE_AD<2> IOSTANDARD = PCI33_3;
 494 #Net fpga_0_PCI32_BRIDGE_AD<2> BYPASS;
 495 #Net fpga_0_PCI32_BRIDGE_AD<1> LOC=L5;
 496 #Net fpga_0_PCI32_BRIDGE_AD<1> IOSTANDARD = PCI33_3;
 497 #Net fpga_0_PCI32_BRIDGE_AD<1> BYPASS;
 498 #Net fpga_0_PCI32_BRIDGE_AD<0> LOC=L4;
 499 #Net fpga_0_PCI32_BRIDGE_AD<0> IOSTANDARD = PCI33_3;
 500 #Net fpga_0_PCI32_BRIDGE_AD<0> BYPASS;
 501 #Net fpga_0_PCI32_BRIDGE_CBE<3> LOC=R6;
 502 #Net fpga_0_PCI32_BRIDGE_CBE<3> IOSTANDARD = PCI33_3;
 503 #Net fpga_0_PCI32_BRIDGE_CBE<3> BYPASS;
 504 #Net fpga_0_PCI32_BRIDGE_CBE<2> LOC=R4;
 505 #Net fpga_0_PCI32_BRIDGE_CBE<2> IOSTANDARD = PCI33_3;
 506 #Net fpga_0_PCI32_BRIDGE_CBE<2> BYPASS;
 507 #Net fpga_0_PCI32_BRIDGE_CBE<1> LOC=L6;
 508 #Net fpga_0_PCI32_BRIDGE_CBE<1> IOSTANDARD = PCI33_3;
 509 #Net fpga_0_PCI32_BRIDGE_CBE<1> BYPASS;
 510 #Net fpga_0_PCI32_BRIDGE_CBE<0> LOC=M5;
 511 #Net fpga_0_PCI32_BRIDGE_CBE<0> IOSTANDARD = PCI33_3;
 512 #Net fpga_0_PCI32_BRIDGE_CBE<0> BYPASS;
 513 #
 514 ##### Module SysACE_CompactFlash constraints
 515 #
 516 #Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF16;
 517 #Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 29000 ps;
 518 #Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin LOC=AD4;
 519 #Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin IOSTANDARD = LVCMOS33;
 520 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AE6;
 521 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS33;
 522 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AE4;
 523 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33;
 524 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AE3;
 525 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33;
 526 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AF6;
 527 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33;
 528 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AF5;
 529 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33;
 530 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AF4;
 531 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33;
 532 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AF3;
 533 #Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33;
 534 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AG6;
 535 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33;
 536 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AG5;
 537 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33;
 538 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG3;
 539 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33;
 540 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AH5;
 541 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33;
 542 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AH4;
 543 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33;
 544 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AH3;
 545 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33;
 546 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AJ6;
 547 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33;
 548 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AJ5;
 549 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33;
 550 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ4;
 551 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33;
 552 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AK6;
 553 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33;
 554 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AK4;
 555 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33;
 556 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AK3;
 557 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33;
 558 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AL6;
 559 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33;
 560 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AL5;
 561 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33;
 562 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AL4;
 563 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33;
 564 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA3;
 565 #Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33;
 566 #Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB6;
 567 #Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33;
 568 #Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AM5;
 569 #Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33;
 570 #Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AB3;
 571 #Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33;
 572 #Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AM6;
 573 #Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33;
 574 #
 575 ##### Module IIC_Bus constraints
 576 #
 577 #Net fpga_0_IIC_Bus_Scl_pin LOC=E7;
 578 #Net fpga_0_IIC_Bus_Scl_pin IOSTANDARD = LVCMOS33;
 579 #Net fpga_0_IIC_Bus_Sda_pin LOC=D7;
 580 #Net fpga_0_IIC_Bus_Sda_pin IOSTANDARD = LVCMOS33;
 581 #
 582 ##### Module ORGate_1 constraints
 583 #
 584 #Net fpga_0_ORGate_1_Res_pin LOC=AE18;
 585 #Net fpga_0_ORGate_1_Res_pin TIG;
 586 #Net fpga_0_ORGate_1_Res_1_pin LOC=AE17;
 587 #Net fpga_0_ORGate_1_Res_1_pin TIG;
 588 #Net fpga_0_ORGate_1_Res_2_pin LOC=R11;
 589 #Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3;
 590 #
 591 ##### Module TriMode_MAC_GMII constraints
 592 #
 593 #Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin LOC = M12;
 594 #Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin IOSTANDARD=LVCMOS33;
 595 #Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin TIG;
 596 #
 597 ##### Module Hard_Temac_0 constraints
 598 #
 599 #Net fpga_0_Hard_Temac_0_MII_TXD_0<3> LOC = K9;
 600 #Net fpga_0_Hard_Temac_0_MII_TXD_0<3> IOSTANDARD=LVCMOS33;
 601 #Net fpga_0_Hard_Temac_0_MII_TXD_0<3> SLEW=FAST;
 602 #Net fpga_0_Hard_Temac_0_MII_TXD_0<2> LOC = K11;
 603 #Net fpga_0_Hard_Temac_0_MII_TXD_0<2> IOSTANDARD=LVCMOS33;
 604 #Net fpga_0_Hard_Temac_0_MII_TXD_0<2> SLEW=FAST;
 605 #Net fpga_0_Hard_Temac_0_MII_TXD_0<1> LOC = K12;
 606 #Net fpga_0_Hard_Temac_0_MII_TXD_0<1> IOSTANDARD=LVCMOS33;
 607 #Net fpga_0_Hard_Temac_0_MII_TXD_0<1> SLEW=FAST;
 608 #Net fpga_0_Hard_Temac_0_MII_TXD_0<0> LOC = K13;
 609 #Net fpga_0_Hard_Temac_0_MII_TXD_0<0> IOSTANDARD=LVCMOS33;
 610 #Net fpga_0_Hard_Temac_0_MII_TXD_0<0> SLEW=FAST;
 611 #Net fpga_0_Hard_Temac_0_MII_TX_EN_0 LOC = L11;
 612 #Net fpga_0_Hard_Temac_0_MII_TX_EN_0 IOSTANDARD=LVCMOS33;
 613 #Net fpga_0_Hard_Temac_0_MII_TX_EN_0 SLEW=FAST;
 614 #Net fpga_0_Hard_Temac_0_MII_TX_ER_0 LOC = L14;
 615 #Net fpga_0_Hard_Temac_0_MII_TX_ER_0 IOSTANDARD=LVCMOS25;
 616 #Net fpga_0_Hard_Temac_0_MII_RXD_0<3> LOC = J9;
 617 #Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOSTANDARD=LVCMOS33;
 618 #Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOBDELAY = NONE;
 619 #Net fpga_0_Hard_Temac_0_MII_RXD_0<2> LOC = J10;
 620 #Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOSTANDARD=LVCMOS33;
 621 #Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOBDELAY = NONE;
 622 #Net fpga_0_Hard_Temac_0_MII_RXD_0<1> LOC = J11;
 623 #Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOSTANDARD=LVCMOS33;
 624 #Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOBDELAY = NONE;
 625 #Net fpga_0_Hard_Temac_0_MII_RXD_0<0> LOC = J12;
 626 #Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOSTANDARD=LVCMOS33;
 627 #Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOBDELAY = NONE;
 628 #Net fpga_0_Hard_Temac_0_MII_RX_DV_0 LOC = H12;
 629 #Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOSTANDARD=LVCMOS33;
 630 #Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOBDELAY = NONE;
 631 #Net fpga_0_Hard_Temac_0_MII_RX_ER_0 LOC = H18;
 632 #Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOSTANDARD=LVCMOS25;
 633 #Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOBDELAY = NONE;
 634 #Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 LOC=J14;
 635 #Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 MAXSKEW= 2.0 ns;
 636 #Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 IOSTANDARD=LVCMOS25;
 637 #Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 LOC=K19;
 638 #Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 MAXSKEW= 2.0 ns;
 639 #Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 IOSTANDARD=LVCMOS25;
 640 #Net fpga_0_Hard_Temac_0_MDIO_0_pin LOC = L13;
 641 #Net fpga_0_Hard_Temac_0_MDIO_0_pin IOSTANDARD=LVCMOS33;
 642 #Net fpga_0_Hard_Temac_0_MDC_0_pin LOC = M13;
 643 #Net fpga_0_Hard_Temac_0_MDC_0_pin IOSTANDARD=LVCMOS33;
 644 #
 645 #Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB;
 646 #TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps;
 647 #
 648 ##### AR 22677
 649 #
 650 #AREA_GROUP "opb2plb" RANGE=SLICE_X20Y104:SLICE_X33Y139, SLICE_X34Y96:SLICE_X51Y139;
 651 #INST "opb2plb" AREA_GROUP = "opb2plb";
 652 #AREA_GROUP "pblock_spi_eeprom" RANGE=SLICE_X54Y92:SLICE_X67Y111;
 653 #INST "spi_eeprom" AREA_GROUP = "pblock_spi_eeprom";
 654 #AREA_GROUP "pblock_plb2opb" RANGE= SLICE_X34Y140:SLICE_X51Y191;
 655 #INST "plb2opb" AREA_GROUP = "pblock_plb2opb";
 656 ## These two items here no longer exist in 8.2i
 657 ## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CARRY_MUX*" AREA_GROUP = "pblock_plb2opb";
 658 ## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CYMUX_FIRST*" AREA_GROUP = "pblock_plb2opb";
 659 #
 660 ## The path "I_PLB_ADDRPATH/I_PLBADDR_MUX" doesn't exist either; using *? to replace it
 661 ## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/_n*" AREA_GROUP = "pblock_plb2opb";
 662 #INST "plb/plb/*?/_n*" AREA_GROUP = "pblock_plb2opb";
 663 #INST "plb/plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/*" AREA_GROUP = "pblock_plb2opb";
 664 #
 665 ###################################
 666 #### Virtex-4 FX60-FF1152 MGT Null Tile LOCs ###
 667 ###################################
 668 ##MGT113A
 669 #INST MGT113AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y7;
 670 #NET "MGT113AB_TXN<1>" LOC = "A3"; #TXN
 671 #NET "MGT113AB_TXP<1>" LOC = "A4"; #TXP
 672 #NET "MGT113AB_RXN<1>" LOC = "A6"; #RXN
 673 #NET "MGT113AB_RXP<1>" LOC = "A7"; #RXP
 674 ##MGT113B
 675 #INST MGT113AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y6;
 676 #NET "MGT113AB_TXN<0>" LOC = "D1"; #TXN
 677 #NET "MGT113AB_TXP<0>" LOC = "C1"; #TXP
 678 #NET "MGT113AB_RXN<0>" LOC = "G1"; #RXN
 679 #NET "MGT113AB_RXP<0>" LOC = "F1"; #RXP
 680 ##MGT112A
 681 #INST MGT112AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y5;
 682 #NET "MGT112AB_TXN<1>" LOC = "T1"; #TXN
 683 #NET "MGT112AB_TXP<1>" LOC = "R1"; #TXP
 684 #NET "MGT112AB_RXN<1>" LOC = "N1"; #RXN
 685 #NET "MGT112AB_RXP<1>" LOC = "M1"; #RXP
 686 ##MGT112B
 687 #INST MGT112AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y4;
 688 #NET "MGT112AB_TXN<0>" LOC = "V1"; #TXN
 689 #NET "MGT112AB_TXP<0>" LOC = "U1"; #TXP
 690 #NET "MGT112AB_RXN<0>" LOC = "AA1"; #RXN
 691 #NET "MGT112AB_RXP<0>" LOC = "Y1"; #RXP
 692 ##MGT110A
 693 #INST MGT110AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y3;
 694 #NET "MGT110AB_TXN<1>" LOC = "AG1"; #TXN
 695 #NET "MGT110AB_TXP<1>" LOC = "AF1"; #TXP
 696 #NET "MGT110AB_RXN<1>" LOC = "AD1"; #RXN
 697 #NET "MGT110AB_RXP<1>" LOC = "AC1"; #RXP
 698 ##MGT110B
 699 #INST MGT110AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y2;
 700 #NET "MGT110AB_TXN<0>" LOC = "AJ1"; #TXN
 701 #NET "MGT110AB_TXP<0>" LOC = "AH1"; #TXP
 702 #NET "MGT110AB_RXN<0>" LOC = "AM1"; #RXN
 703 #NET "MGT110AB_RXP<0>" LOC = "AL1"; #RXP
 704 ##MGT109A
 705 #INST MGT109AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y1;
 706 #NET "MGT109AB_TXN<1>" LOC = "AP10"; #TXN
 707 #NET "MGT109AB_TXP<1>" LOC = "AP9"; #TXP
 708 #NET "MGT109AB_RXN<1>" LOC = "AP7"; #RXN
 709 #NET "MGT109AB_RXP<1>" LOC = "AP6"; #RXP
 710 ##MGT109B
 711 #INST MGT109AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y0;
 712 #NET "MGT109AB_TXN<0>" LOC = "AP12"; #TXN
 713 #NET "MGT109AB_TXP<0>" LOC = "AP11"; #TXP
 714 #NET "MGT109AB_RXN<0>" LOC = "AP15"; #RXN
 715 #NET "MGT109AB_RXP<0>" LOC = "AP14"; #RXP
 716 ##MGT102A
 717 #INST MGT102AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y7;
 718 #NET "MGT102AB_TXN<1>" LOC = "E34"; #TXN
 719 #NET "MGT102AB_TXP<1>" LOC = "D34"; #TXP
 720 #NET "MGT102AB_RXN<1>" LOC = "A32"; #RXN
 721 #NET "MGT102AB_RXP<1>" LOC = "A31"; #RXP
 722 #
 723 ##MGT102B
 724 #INST MGT102AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y6;
 725 #NET "MGT102AB_TXN<0>" LOC = "G34"; #TXN
 726 #NET "MGT102AB_TXP<0>" LOC = "F34"; #TXP
 727 #NET "MGT102AB_RXN<0>" LOC = "K34"; #RXN
 728 #NET "MGT102AB_RXP<0>" LOC = "J34"; #RXP
 729 ##MGT103A
 730 #INST MGT103AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y5;
 731 #NET "MGT103AB_TXN<1>" LOC = "W34"; #TXN
 732 #NET "MGT103AB_TXP<1>" LOC = "V34"; #TXP
 733 #NET "MGT103AB_RXN<1>" LOC = "T34"; #RXN
 734 #NET "MGT103AB_RXP<1>" LOC = "R34"; #RXP
 735 ##MGT103B
 736 #INST MGT103AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y4;
 737 #NET "MGT103AB_TXN<0>" LOC = "AA34"; #TXN
 738 #NET "MGT103AB_TXP<0>" LOC = "Y34"; #TXP
 739 #NET "MGT103AB_RXN<0>" LOC = "AD34"; #RXN
 740 #NET "MGT103AB_RXP<0>" LOC = "AC34"; #RXP
 741 ##MGT105A
 742 #INST MGT105AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y3;
 743 #NET "MGT105AB_TXN<1>" LOC = "AK34"; #TXN
 744 #NET "MGT105AB_TXP<1>" LOC = "AJ34"; #TXP
 745 #NET "MGT105AB_RXN<1>" LOC = "AG34"; #RXN
 746 #NET "MGT105AB_RXP<1>" LOC = "AF34"; #RXP
 747 ##MGT105B
 748 #INST MGT105AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y2;
 749 #NET "MGT105AB_TXN<0>" LOC = "AM34"; #TXN
 750 #NET "MGT105AB_TXP<0>" LOC = "AL34"; #TXP
 751 #NET "MGT105AB_RXN<0>" LOC = "AP31"; #RXN
 752 #NET "MGT105AB_RXP<0>" LOC = "AP32"; #RXP
 753 ##MGT106A
 754 #INST MGT106AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y1;
 755 #NET "MGT106AB_TXN<1>" LOC = "AP22"; #TXN
 756 #NET "MGT106AB_TXP<1>" LOC = "AP23"; #TXP
 757 #NET "MGT106AB_RXN<1>" LOC = "AP25"; #RXN
 758 #NET "MGT106AB_RXP<1>" LOC = "AP26"; #RXP
 759 ##MGT106B
 760 #INST MGT106AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y0;
 761 #NET "MGT106AB_TXN<0>" LOC = "AP20"; #TXN
 762 #NET "MGT106AB_TXP<0>" LOC = "AP21"; #TXP
 763 #NET "MGT106AB_RXN<0>" LOC = "AP17"; #RXN
 764 #NET "MGT106AB_RXP<0>" LOC = "AP18"; #RXP
 765 #
 766
 767
 768
 769 ## DDR ##############################################################################
 770
 771
 772 ## IO Devices constraints
 773
 774 #### Module ORGate_1 constraints
 775
 776 # Net fpga_0_ORGate_1_Res_pin LOC=AE18;
 777 # Net fpga_0_ORGate_1_Res_pin TIG;
 778 # Net fpga_0_ORGate_1_Res_1_pin LOC=AE17;
 779 # Net fpga_0_ORGate_1_Res_1_pin TIG;
 780 # Net fpga_0_ORGate_1_Res_2_pin LOC=R11;
 781 # Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3;
 782
 783 #### Module DDR2_SDRAM constraints
 784
 785 # Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin LOC=AA25;
 786 # Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin IOSTANDARD = SSTL18_I;
 787 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> LOC=H28;
 788 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> IOSTANDARD = SSTL18_I;
 789 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> LOC=K28;
 790 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> IOSTANDARD = SSTL18_I;
 791 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> LOC=L28;
 792 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> IOSTANDARD = SSTL18_I;
 793 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> LOC=M25;
 794 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> IOSTANDARD = SSTL18_I;
 795 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> LOC=Y24;
 796 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> IOSTANDARD = SSTL18_I;
 797 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> LOC=N27;
 798 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> IOSTANDARD = SSTL18_I;
 799 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> LOC=AD26;
 800 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> IOSTANDARD = SSTL18_I;
 801 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> LOC=AC25;
 802 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> IOSTANDARD = SSTL18_I;
 803 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> LOC=R26;
 804 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> IOSTANDARD = SSTL18_I;
 805 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> LOC=R28;
 806 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> IOSTANDARD = SSTL18_I;
 807 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> LOC=T26;
 808 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> IOSTANDARD = SSTL18_I;
 809 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> LOC=T28;
 810 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> IOSTANDARD = SSTL18_I;
 811 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> LOC=U27;
 812 # Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> IOSTANDARD = SSTL18_I;
 813 # Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> LOC=V28;
 814 # Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> IOSTANDARD = SSTL18_I;
 815 # Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> LOC=W26;
 816 # Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> IOSTANDARD = SSTL18_I;
 817 # Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin LOC=R31;
 818 # Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin IOSTANDARD = SSTL18_I;
 819 # Net fpga_0_DDR2_SDRAM_DDR2_CE_pin LOC=AJ31;
 820 # Net fpga_0_DDR2_SDRAM_DDR2_CE_pin IOSTANDARD = SSTL18_I;
 821 # Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin LOC=AJ30;
 822 # Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin IOSTANDARD = SSTL18_I;
 823 # Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin LOC=R32;
 824 # Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin IOSTANDARD = SSTL18_I;
 825 # Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin LOC=T31;
 826 # Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin IOSTANDARD = SSTL18_I;
 827 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AH30;
 828 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> IOSTANDARD = SSTL18_II;
 829 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=M31;
 830 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> IOSTANDARD = SSTL18_II;
 831 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=T30;
 832 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> IOSTANDARD = SSTL18_II;
 833 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=U28;
 834 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> IOSTANDARD = SSTL18_II;
 835 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=AJ32;
 836 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> IOSTANDARD = SSTL18_II;
 837 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=AG31;
 838 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> IOSTANDARD = SSTL18_II;
 839 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=AG30;
 840 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> IOSTANDARD = SSTL18_II;
 841 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=AF29;
 842 # Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> IOSTANDARD = SSTL18_II;
 843 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<0> LOC=F29;
 844 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<0> IOSTANDARD = SSTL18_II;
 845 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<1> LOC=K29;
 846 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<1> IOSTANDARD = SSTL18_II;
 847 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<2> LOC=P27;
 848 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<2> IOSTANDARD = SSTL18_II;
 849 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<3> LOC=P32;
 850 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<3> IOSTANDARD = SSTL18_II;
 851 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<4> LOC=W27;
 852 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<4> IOSTANDARD = SSTL18_II;
 853 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<5> LOC=W31;
 854 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<5> IOSTANDARD = SSTL18_II;
 855 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<6> LOC=AG32;
 856 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<6> IOSTANDARD = SSTL18_II;
 857 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<7> LOC=AE32;
 858 # Net fpga_0_DDR2_SDRAM_DDR2_DQS<7> IOSTANDARD = SSTL18_II;
 859 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<0> LOC=E29;
 860 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<0> IOSTANDARD = SSTL18_II;
 861 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<1> LOC=J29;
 862 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<1> IOSTANDARD = SSTL18_II;
 863 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<2> LOC=P26;
 864 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<2> IOSTANDARD = SSTL18_II;
 865 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<3> LOC=N32;
 866 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<3> IOSTANDARD = SSTL18_II;
 867 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<4> LOC=V27;
 868 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<4> IOSTANDARD = SSTL18_II;
 869 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<5> LOC=W30;
 870 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<5> IOSTANDARD = SSTL18_II;
 871 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<6> LOC=AH32;
 872 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<6> IOSTANDARD = SSTL18_II;
 873 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<7> LOC=AE31;
 874 # Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<7> IOSTANDARD = SSTL18_II;
 875 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<0> LOC=C32;
 876 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<0> IOSTANDARD = SSTL18_II;
 877 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<1> LOC=D32;
 878 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<1> IOSTANDARD = SSTL18_II;
 879 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<2> LOC=E32;
 880 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<2> IOSTANDARD = SSTL18_II;
 881 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<3> LOC=G32;
 882 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<3> IOSTANDARD = SSTL18_II;
 883 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<4> LOC=H32;
 884 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<4> IOSTANDARD = SSTL18_II;
 885 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<5> LOC=J32;
 886 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<5> IOSTANDARD = SSTL18_II;
 887 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<6> LOC=K32;
 888 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<6> IOSTANDARD = SSTL18_II;
 889 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<7> LOC=M32;
 890 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<7> IOSTANDARD = SSTL18_II;
 891 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<8> LOC=N28;
 892 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<8> IOSTANDARD = SSTL18_II;
 893 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<9> LOC=D31;
 894 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<9> IOSTANDARD = SSTL18_II;
 895 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<10> LOC=E31;
 896 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<10> IOSTANDARD = SSTL18_II;
 897 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<11> LOC=F31;
 898 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<11> IOSTANDARD = SSTL18_II;
 899 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<12> LOC=G31;
 900 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<12> IOSTANDARD = SSTL18_II;
 901 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<13> LOC=J31;
 902 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<13> IOSTANDARD = SSTL18_II;
 903 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<14> LOC=K31;
 904 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<14> IOSTANDARD = SSTL18_II;
 905 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<15> LOC=L31;
 906 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<15> IOSTANDARD = SSTL18_II;
 907 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<16> LOC=C30;
 908 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<16> IOSTANDARD = SSTL18_II;
 909 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<17> LOC=D30;
 910 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<17> IOSTANDARD = SSTL18_II;
 911 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<18> LOC=F30;
 912 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<18> IOSTANDARD = SSTL18_II;
 913 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<19> LOC=G30;
 914 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<19> IOSTANDARD = SSTL18_II;
 915 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<20> LOC=Y28;
 916 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<20> IOSTANDARD = SSTL18_II;
 917 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<21> LOC=Y27;
 918 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<21> IOSTANDARD = SSTL18_II;
 919 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<22> LOC=L30;
 920 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<22> IOSTANDARD = SSTL18_II;
 921 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<23> LOC=M30;
 922 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<23> IOSTANDARD = SSTL18_II;
 923 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<24> LOC=N30;
 924 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<24> IOSTANDARD = SSTL18_II;
 925 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<25> LOC=C29;
 926 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<25> IOSTANDARD = SSTL18_II;
 927 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<26> LOC=D29;
 928 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<26> IOSTANDARD = SSTL18_II;
 929 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<27> LOC=J30;
 930 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<27> IOSTANDARD = SSTL18_II;
 931 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<28> LOC=L29;
 932 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<28> IOSTANDARD = SSTL18_II;
 933 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<29> LOC=N29;
 934 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<29> IOSTANDARD = SSTL18_II;
 935 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<30> LOC=P29;
 936 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<30> IOSTANDARD = SSTL18_II;
 937 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<31> LOC=R29;
 938 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<31> IOSTANDARD = SSTL18_II;
 939 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<32> LOC=T29;
 940 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<32> IOSTANDARD = SSTL18_II;
 941 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<33> LOC=U32;
 942 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<33> IOSTANDARD = SSTL18_II;
 943 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<34> LOC=V32;
 944 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<34> IOSTANDARD = SSTL18_II;
 945 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<35> LOC=W32;
 946 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<35> IOSTANDARD = SSTL18_II;
 947 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<36> LOC=Y32;
 948 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<36> IOSTANDARD = SSTL18_II;
 949 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<37> LOC=AB32;
 950 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<37> IOSTANDARD = SSTL18_II;
 951 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<38> LOC=AC32;
 952 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<38> IOSTANDARD = SSTL18_II;
 953 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<39> LOC=AD32;
 954 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<39> IOSTANDARD = SSTL18_II;
 955 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<40> LOC=AB27;
 956 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<40> IOSTANDARD = SSTL18_II;
 957 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<41> LOC=U31;
 958 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<41> IOSTANDARD = SSTL18_II;
 959 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<42> LOC=W25;
 960 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<42> IOSTANDARD = SSTL18_II;
 961 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<43> LOC=Y31;
 962 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<43> IOSTANDARD = SSTL18_II;
 963 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<44> LOC=AA31;
 964 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<44> IOSTANDARD = SSTL18_II;
 965 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<45> LOC=AB31;
 966 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<45> IOSTANDARD = SSTL18_II;
 967 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<46> LOC=AD31;
 968 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<46> IOSTANDARD = SSTL18_II;
 969 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<47> LOC=AB28;
 970 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<47> IOSTANDARD = SSTL18_II;
 971 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<48> LOC=AF31;
 972 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<48> IOSTANDARD = SSTL18_II;
 973 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<49> LOC=U30;
 974 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<49> IOSTANDARD = SSTL18_II;
 975 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<50> LOC=V30;
 976 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<50> IOSTANDARD = SSTL18_II;
 977 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<51> LOC=Y26;
 978 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<51> IOSTANDARD = SSTL18_II;
 979 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<52> LOC=AA30;
 980 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<52> IOSTANDARD = SSTL18_II;
 981 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<53> LOC=AB30;
 982 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<53> IOSTANDARD = SSTL18_II;
 983 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<54> LOC=AC30;
 984 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<54> IOSTANDARD = SSTL18_II;
 985 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<55> LOC=AD30;
 986 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<55> IOSTANDARD = SSTL18_II;
 987 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<56> LOC=AF30;
 988 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<56> IOSTANDARD = SSTL18_II;
 989 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<57> LOC=V29;
 990 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<57> IOSTANDARD = SSTL18_II;
 991 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<58> LOC=W29;
 992 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<58> IOSTANDARD = SSTL18_II;
 993 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<59> LOC=Y29;
 994 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<59> IOSTANDARD = SSTL18_II;
 995 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<60> LOC=AA29;
 996 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<60> IOSTANDARD = SSTL18_II;
 997 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<61> LOC=AC29;
 998 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<61> IOSTANDARD = SSTL18_II;
 999 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<62> LOC=AD29;
1000 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<62> IOSTANDARD = SSTL18_II;
1001 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<63> LOC=AE29;
1002 # Net fpga_0_DDR2_SDRAM_DDR2_DQ<63> IOSTANDARD = SSTL18_II;
1003 # Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin LOC=H30;
1004 # Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin IOSTANDARD = DIFF_SSTL18_II;
1005 # Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin LOC=H29;
1006 # Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin IOSTANDARD = DIFF_SSTL18_II;
1007
1008 #### Module DDR_SDRAM constraints
1009
1010 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=J24;
1011 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
1012 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=K26;
1013 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
1014 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=K24;
1015 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
1016 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=K23;
1017 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
1018 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=L26;
1019 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
1020 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=L25;
1021 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
1022 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=L24;
1023 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
1024 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=M23;
1025 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
1026 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=N24;
1027 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
1028 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=N23;
1029 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
1030 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=N22;
1031 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
1032 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=P22;
1033 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
1034 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=P24;
1035 Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
1036 Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=J26;
1037 Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
1038 Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=J25;
1039 Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
1040 Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=D26;
1041 Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I;
1042 Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=H14;
1043 Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I;
1044 Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=C27;
1045 Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I;
1046 Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=D27;
1047 Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I;
1048 Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=E27;
1049 Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I;
1050 Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=F21;
1051 Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
1052 Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=G22;
1053 Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
1054 Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> LOC=E23;
1055 Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
1056 Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> LOC=G23;
1057 Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
1058 Net fpga_0_DDR_SDRAM_DDR_DQS<0> LOC=F20;
1059 Net fpga_0_DDR_SDRAM_DDR_DQS<0> IOSTANDARD = SSTL2_II;
1060 Net fpga_0_DDR_SDRAM_DDR_DQS<1> LOC=G20;
1061 Net fpga_0_DDR_SDRAM_DDR_DQS<1> IOSTANDARD = SSTL2_II;
1062 Net fpga_0_DDR_SDRAM_DDR_DQS<2> LOC=G25;
1063 Net fpga_0_DDR_SDRAM_DDR_DQS<2> IOSTANDARD = SSTL2_II;
1064 Net fpga_0_DDR_SDRAM_DDR_DQS<3> LOC=F25;
1065 Net fpga_0_DDR_SDRAM_DDR_DQS<3> IOSTANDARD = SSTL2_II;
1066 Net fpga_0_DDR_SDRAM_DDR_DQ<0> LOC=E17;
1067 Net fpga_0_DDR_SDRAM_DDR_DQ<0> IOSTANDARD = SSTL2_II;
1068 Net fpga_0_DDR_SDRAM_DDR_DQ<1> LOC=E18;
1069 Net fpga_0_DDR_SDRAM_DDR_DQ<1> IOSTANDARD = SSTL2_II;
1070 Net fpga_0_DDR_SDRAM_DDR_DQ<2> LOC=F18;
1071 Net fpga_0_DDR_SDRAM_DDR_DQ<2> IOSTANDARD = SSTL2_II;
1072 Net fpga_0_DDR_SDRAM_DDR_DQ<3> LOC=G18;
1073 Net fpga_0_DDR_SDRAM_DDR_DQ<3> IOSTANDARD = SSTL2_II;
1074 Net fpga_0_DDR_SDRAM_DDR_DQ<4> LOC=F19;
1075 Net fpga_0_DDR_SDRAM_DDR_DQ<4> IOSTANDARD = SSTL2_II;
1076 Net fpga_0_DDR_SDRAM_DDR_DQ<5> LOC=E19;
1077 Net fpga_0_DDR_SDRAM_DDR_DQ<5> IOSTANDARD = SSTL2_II;
1078 Net fpga_0_DDR_SDRAM_DDR_DQ<6> LOC=D21;
1079 Net fpga_0_DDR_SDRAM_DDR_DQ<6> IOSTANDARD = SSTL2_II;
1080 Net fpga_0_DDR_SDRAM_DDR_DQ<7> LOC=E21;
1081 Net fpga_0_DDR_SDRAM_DDR_DQ<7> IOSTANDARD = SSTL2_II;
1082 Net fpga_0_DDR_SDRAM_DDR_DQ<8> LOC=G21;
1083 Net fpga_0_DDR_SDRAM_DDR_DQ<8> IOSTANDARD = SSTL2_II;
1084 Net fpga_0_DDR_SDRAM_DDR_DQ<9> LOC=H20;
1085 Net fpga_0_DDR_SDRAM_DDR_DQ<9> IOSTANDARD = SSTL2_II;
1086 Net fpga_0_DDR_SDRAM_DDR_DQ<10> LOC=J20;
1087 Net fpga_0_DDR_SDRAM_DDR_DQ<10> IOSTANDARD = SSTL2_II;
1088 Net fpga_0_DDR_SDRAM_DDR_DQ<11> LOC=J21;
1089 Net fpga_0_DDR_SDRAM_DDR_DQ<11> IOSTANDARD = SSTL2_II;
1090 Net fpga_0_DDR_SDRAM_DDR_DQ<12> LOC=K21;
1091 Net fpga_0_DDR_SDRAM_DDR_DQ<12> IOSTANDARD = SSTL2_II;
1092 Net fpga_0_DDR_SDRAM_DDR_DQ<13> LOC=L21;
1093 Net fpga_0_DDR_SDRAM_DDR_DQ<13> IOSTANDARD = SSTL2_II;
1094 Net fpga_0_DDR_SDRAM_DDR_DQ<14> LOC=J22;
1095 Net fpga_0_DDR_SDRAM_DDR_DQ<14> IOSTANDARD = SSTL2_II;
1096 Net fpga_0_DDR_SDRAM_DDR_DQ<15> LOC=H22;
1097 Net fpga_0_DDR_SDRAM_DDR_DQ<15> IOSTANDARD = SSTL2_II;
1098 Net fpga_0_DDR_SDRAM_DDR_DQ<16> LOC=C22;
1099 Net fpga_0_DDR_SDRAM_DDR_DQ<16> IOSTANDARD = SSTL2_II;
1100 Net fpga_0_DDR_SDRAM_DDR_DQ<17> LOC=C23;
1101 Net fpga_0_DDR_SDRAM_DDR_DQ<17> IOSTANDARD = SSTL2_II;
1102 Net fpga_0_DDR_SDRAM_DDR_DQ<18> LOC=C24;
1103 Net fpga_0_DDR_SDRAM_DDR_DQ<18> IOSTANDARD = SSTL2_II;
1104 Net fpga_0_DDR_SDRAM_DDR_DQ<19> LOC=C25;
1105 Net fpga_0_DDR_SDRAM_DDR_DQ<19> IOSTANDARD = SSTL2_II;
1106 Net fpga_0_DDR_SDRAM_DDR_DQ<20> LOC=D22;
1107 Net fpga_0_DDR_SDRAM_DDR_DQ<20> IOSTANDARD = SSTL2_II;
1108 Net fpga_0_DDR_SDRAM_DDR_DQ<21> LOC=D24;
1109 Net fpga_0_DDR_SDRAM_DDR_DQ<21> IOSTANDARD = SSTL2_II;
1110 Net fpga_0_DDR_SDRAM_DDR_DQ<22> LOC=D25;
1111 Net fpga_0_DDR_SDRAM_DDR_DQ<22> IOSTANDARD = SSTL2_II;
1112 Net fpga_0_DDR_SDRAM_DDR_DQ<23> LOC=C28;
1113 Net fpga_0_DDR_SDRAM_DDR_DQ<23> IOSTANDARD = SSTL2_II;
1114 Net fpga_0_DDR_SDRAM_DDR_DQ<24> LOC=F23;
1115 Net fpga_0_DDR_SDRAM_DDR_DQ<24> IOSTANDARD = SSTL2_II;
1116 Net fpga_0_DDR_SDRAM_DDR_DQ<25> LOC=F24;
1117 Net fpga_0_DDR_SDRAM_DDR_DQ<25> IOSTANDARD = SSTL2_II;
1118 Net fpga_0_DDR_SDRAM_DDR_DQ<26> LOC=F26;
1119 Net fpga_0_DDR_SDRAM_DDR_DQ<26> IOSTANDARD = SSTL2_II;
1120 Net fpga_0_DDR_SDRAM_DDR_DQ<27> LOC=G26;
1121 Net fpga_0_DDR_SDRAM_DDR_DQ<27> IOSTANDARD = SSTL2_II;
1122 Net fpga_0_DDR_SDRAM_DDR_DQ<28> LOC=H25;
1123 Net fpga_0_DDR_SDRAM_DDR_DQ<28> IOSTANDARD = SSTL2_II;
1124 Net fpga_0_DDR_SDRAM_DDR_DQ<29> LOC=H24;
1125 Net fpga_0_DDR_SDRAM_DDR_DQ<29> IOSTANDARD = SSTL2_II;
1126 Net fpga_0_DDR_SDRAM_DDR_DQ<30> LOC=E24;
1127 Net fpga_0_DDR_SDRAM_DDR_DQ<30> IOSTANDARD = SSTL2_II;
1128 Net fpga_0_DDR_SDRAM_DDR_DQ<31> LOC=E22;
1129 Net fpga_0_DDR_SDRAM_DDR_DQ<31> IOSTANDARD = SSTL2_II;
1130 Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=F28;
1131 Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = SSTL2_II;
1132 Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=E28;
1133 Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = SSTL2_II;