src/edu/berkeley/fleet/fpga/main.v

   1
   2 module main
   3  (sys_clk_pin,   /* 100Mhz */
   4   sys_rst_pin,
   5   fpga_0_RS232_Uart_1_ctsN_pin,
   6   fpga_0_RS232_Uart_1_rtsN_pin,
   7   fpga_0_RS232_Uart_1_sin_pin,
   8   fpga_0_RS232_Uart_1_sout_pin,
   9
  10   ddr1_Clk_pin,
  11   ddr1_Clk_n_pin,
  12   ddr1_Addr_pin,
  13   ddr1_BankAddr_pin,
  14   ddr1_CAS_n_pin,
  15   ddr1_CE_pin,
  16   ddr1_CS_n_pin,
  17   ddr1_RAS_n_pin,
  18   ddr1_WE_n_pin,
  19   ddr1_DM_pin,
  20   ddr1_DQS,
  21   ddr1_DQ,
  22 /*
  23   ddr2_ODT_pin,
  24   ddr2_Clk_pin,
  25   ddr2_Clk_n_pin,
  26   ddr2_Addr_pin,
  27   ddr2_BankAddr_pin,
  28   ddr2_CAS_n_pin,
  29   ddr2_CE_pin,
  30   ddr2_CS_n_pin,
  31   ddr2_RAS_n_pin,
  32   ddr2_WE_n_pin,
  33   ddr2_DM_pin,
  34   ddr2_DQS,
  35   ddr2_DQS_n,
  36   ddr2_DQ,
  37 */
  38   vga_psave,
  39   vga_hsync,
  40   vga_vsync,
  41   vga_sync,
  42   vga_blank,
  43   vga_r,
  44   vga_g,
  45   vga_b,
  46   vga_clkout,
  47
  48   fpga_0_LEDs_8Bit_GPIO_IO_pin
  49  );
  50
  51   input  sys_clk_pin;
  52   input  sys_rst_pin;
  53   input  fpga_0_RS232_Uart_1_ctsN_pin;
  54   output fpga_0_RS232_Uart_1_rtsN_pin;
  55   input  fpga_0_RS232_Uart_1_sin_pin;
  56   output fpga_0_RS232_Uart_1_sout_pin;
  57
  58   output        ddr1_Clk_pin;
  59   output        ddr1_Clk_n_pin;
  60   output [12:0] ddr1_Addr_pin;
  61   output [1:0]  ddr1_BankAddr_pin;
  62   output        ddr1_CAS_n_pin;
  63   output        ddr1_CE_pin;
  64   output        ddr1_CS_n_pin;
  65   output        ddr1_RAS_n_pin;
  66   output        ddr1_WE_n_pin;
  67   output [3:0]  ddr1_DM_pin;
  68   inout  [3:0]  ddr1_DQS;
  69   inout  [31:0] ddr1_DQ;
  70 /*
  71   output        ddr2_ODT_pin;
  72   output        ddr2_Clk_pin;
  73   output        ddr2_Clk_n_pin;
  74   output [12:0] ddr2_Addr_pin;
  75   output [1:0]  ddr2_BankAddr_pin;
  76   output        ddr2_CAS_n_pin;
  77   output        ddr2_CE_pin;
  78   output        ddr2_CS_n_pin;
  79   output        ddr2_RAS_n_pin;
  80   output        ddr2_WE_n_pin;
  81   output [7:0]  ddr2_DM_pin;
  82   inout  [7:0]  ddr2_DQS;
  83   inout  [7:0]  ddr2_DQS_n;
  84   inout  [63:0] ddr2_DQ;
  85 */
  86   wire  [31:0]  dram_addr;
  87   wire          dram_addr_r;
  88   wire          dram_addr_a;
  89   wire          dram_isread;
  90   wire  [63:0]  dram_write_data;
  91   wire          dram_write_data_push;
  92   wire          dram_write_data_full;
  93   wire   [63:0] dram_read_data;
  94   wire          dram_read_data_pop;
  95   wire          dram_read_data_empty;
  96   wire   [1:0]  dram_read_data_latency;
  97
  98 /*
  99   wire  [31:0]  ddr2_addr;
 100   wire          ddr2_addr_r;
 101   wire          ddr2_addr_a;
 102   wire          ddr2_isread;
 103   wire  [63:0]  ddr2_write_data;
 104   wire          ddr2_write_data_push;
 105   wire          ddr2_write_data_full;
 106   wire   [63:0] ddr2_read_data;
 107   wire          ddr2_read_data_pop;
 108   wire          ddr2_read_data_empty;
 109   wire   [1:0]  ddr2_read_data_latency;
 110 */
 111
 112   output vga_psave;
 113   output vga_hsync;
 114   output vga_vsync;
 115   output vga_sync;
 116   output vga_blank;
 117   output [7:0] vga_r;
 118   output [7:0] vga_g;
 119   output [7:0] vga_b;
 120   output vga_clkout;
 121
 122   wire clk;
 123   wire clk_fb;
 124   wire clk50mhz;
 125   wire clk_unbuffered;
 126
 127   wire vga_clk;
 128   wire vga_clk_fb;
 129   wire vga_clk_unbuffered;
 130
 131   output [7:0] fpga_0_LEDs_8Bit_GPIO_IO_pin;
 132   wire [7:0] leds;
 133   assign fpga_0_LEDs_8Bit_GPIO_IO_pin = ~leds;
 134
 135   assign leds[5:0] = dram_read_data[5:0];
 136   assign leds[6] = dram_addr_r;
 137   assign leds[7] = dram_addr_a;
 138
 139   BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));
 140
 141   DCM
 142    #(
 143       .CLKFX_MULTIPLY(4),
 144       .CLKFX_DIVIDE(8),
 145       .CLKIN_PERIOD("10 ns")
 146     ) mydcm(
 147       .CLKIN (sys_clk_pin),
 148       .CLKFB(clk_fb),
 149       .CLKFX (clk_unbuffered),
 150       .CLK0  (clk_fb)
 151     );
 152
 153   BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
 154   DCM  // 25Mhz VGA clock
 155    #(
 156       .CLKFX_MULTIPLY(4),
 157       .CLKFX_DIVIDE(16),
 158       .CLKIN_PERIOD("20 ns")
 159     ) vgadcm (
 160       .CLKIN (clk_unbuffered),
 161       .CLKFB(vga_clk_fb),
 162       .CLKFX (vga_clk_unbuffered),
 163       .CLK0  (vga_clk_fb)
 164     );
 165
 166
 167   wire break_o;
 168   wire break;
 169   reg break_last;
 170   reg send_k;                initial send_k = 0;
 171   wire rst;
 172   assign rst = sys_rst_pin;
 173
 174   wire       data_to_host_full;
 175   wire       data_to_host_write_enable;
 176   wire [7:0] data_to_host;
 177
 178   wire       data_to_fleet_empty;
 179   wire       data_to_fleet_read_enable;
 180   wire [7:0] data_to_fleet;
 181
 182   reg we;
 183   reg re;
 184   reg [7:0] data_to_host_r;
 185   assign data_to_host = data_to_host_r;
 186
 187   wire ser_rst;
 188   reg ser_rst_r;
 189   initial ser_rst_r = 0;
 190   assign ser_rst = (rst & ser_rst_r);
 191
 192   wire sio_ce;
 193   wire sio_ce_x4;
 194
 195   sasc_brg sasc_brg(sys_clk_pin, ser_rst, 8, 65, sio_ce, sio_ce_x4);
 196   sasc_top sasc_top(clk, ser_rst,
 197                     fpga_0_RS232_Uart_1_sin_pin,
 198                     fpga_0_RS232_Uart_1_sout_pin,
 199                     fpga_0_RS232_Uart_1_ctsN_pin,
 200                     fpga_0_RS232_Uart_1_rtsN_pin,
 201                     sio_ce,
 202                     sio_ce_x4,
 203                     data_to_host,
 204                     data_to_fleet,
 205                     data_to_fleet_read_enable,
 206                     data_to_host_write_enable,
 207                     data_to_host_full,
 208                     data_to_fleet_empty,
 209                     break_o,
 210                     break);
 211
 212    // break and break_o are _active high_
 213    always @(posedge clk) break_last <= break_o;
 214    assign break      =  break_o && !break_last;
 215    assign break_done = !break_o &&  break_last;
 216
 217    reg data_to_host_write_enable_reg;
 218    reg data_to_fleet_read_enable_reg;
 219
 220    reg root_out_a_reg;
 221    reg root_in_r_reg;
 222    reg [7:0] root_in_d_reg;
 223    wire root_in_a;
 224    wire root_in_r;
 225    wire root_out_a;
 226    wire root_out_r;
 227    wire [7:0] root_in_d;
 228    wire [7:0] root_out_d;
 229
 230    /*
 231     * There is some very weird timing thing going on here; we need to
 232     * hold reset low for more than one clock in order for it to propagate
 233     * all the way to the docks.
 234     */
 235    root my_root(clk, rst && !break_o,
 236                 root_in_r,  root_in_a,  root_in_d,
 237                 root_out_r, root_out_a, root_out_d,
 238                 dram_addr,
 239                 dram_addr_r,
 240                 dram_addr_a,
 241                 dram_isread,
 242                 dram_write_data,
 243                 dram_write_data_push,
 244                 dram_write_data_full,
 245                 dram_read_data,
 246                 dram_read_data_pop,
 247                 dram_read_data_empty,
 248                 dram_read_data_latency,
 249                 vga_clk,
 250                 vga_psave,
 251                 vga_hsync,
 252                 vga_vsync,
 253                 vga_sync,
 254                 vga_blank,
 255                 vga_r,
 256                 vga_g,
 257                 vga_b,
 258                 vga_clkout
 259                );
 260 /*
 261    fifo4 my_root(clk, rst,
 262                 root_in_r,  root_in_a,  root_in_d,
 263                 root_out_r, root_out_a, data_to_host);
 264 */
 265    assign root_out_a                = root_out_a_reg;
 266    assign root_in_r                 = root_in_r_reg;
 267    assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
 268    assign data_to_host_write_enable = data_to_host_write_enable_reg;
 269    assign root_in_d                 = root_in_d_reg;
 270
 271    // fpga -> host
 272    always @(posedge clk)
 273    begin
 274      if (break) begin
 275        root_out_a_reg = 0;
 276        data_to_host_write_enable_reg <= 0;
 277
 278      end else if (break_done) begin
 279        data_to_host_write_enable_reg <= 1;
 280        data_to_host_r <= 111;
 281        send_k <= 1;
 282      end else if (send_k) begin
 283        data_to_host_write_enable_reg <= 1;
 284        data_to_host_r <= 107;
 285        send_k <= 0;
 286
 287
 288      end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
 289        data_to_host_write_enable_reg <= 1;
 290        data_to_host_r <= root_out_d;
 291        root_out_a_reg = 1;
 292      end else if (root_out_a_reg && !root_out_r) begin
 293        data_to_host_write_enable_reg <= 0;
 294        root_out_a_reg = 0;
 295      end else begin
 296        data_to_host_write_enable_reg <= 0;
 297      end
 298    end
 299
 300    // host -> fpga
 301    always @(posedge clk)
 302    begin
 303      ser_rst_r <= 1;
 304      if (break) begin
 305        root_in_r_reg <= 0;
 306        root_in_d_reg <= 0;
 307        data_to_fleet_read_enable_reg <= 0;
 308      end else
 309
 310      if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
 311         root_in_r_reg <= 1;
 312         root_in_d_reg <= data_to_fleet;
 313         data_to_fleet_read_enable_reg <= 1;
 314      end else begin
 315        data_to_fleet_read_enable_reg <= 0;
 316         if (root_in_a) begin
 317           root_in_r_reg <= 0;
 318         end
 319      end
 320    end
 321
 322    initial
 323    begin
 324      root_in_r_reg = 0;
 325      root_in_d_reg = 0;
 326      root_out_a_reg = 0;
 327      data_to_fleet_read_enable_reg = 0;
 328      data_to_host_write_enable_reg = 0;
 329    end
 330
 331    ddr_ctrl
 332    #(
 333         .clk_freq( 50000000 ),
 334         .clk_multiply( 12 ),
 335         .clk_divide( 5 ),
 336         .phase_shift( 0 ),
 337         .wait200_init( 26 )
 338    ) ddr_ctrl (
 339           .ddr_a( ddr1_Addr_pin ),
 340           .ddr_clk( ddr1_Clk_pin ),
 341           .ddr_clk_n( ddr1_Clk_n_pin ),
 342           .ddr_ba( ddr1_BankAddr_pin ),
 343           .ddr_dq( ddr1_DQ ),
 344           .ddr_dm( ddr1_DM_pin ),
 345           .ddr_dqs( ddr1_DQS ),
 346           .ddr_cs_n( ddr1_CS_n_pin ),
 347           .ddr_ras_n( ddr1_RAS_n_pin ),
 348           .ddr_cas_n( ddr1_CAS_n_pin ),
 349           .ddr_we_n( ddr1_WE_n_pin ),
 350           .ddr_cke( ddr1_CE_pin ),
 351
 352           .clk(clk),
 353           .reset(!rst),
 354           .rot(3'b100),
 355
 356           .fml_wr(!dram_isread && dram_addr_r),
 357           .fml_done(dram_addr_a),
 358           .fml_rd( dram_isread && dram_addr_r),
 359           .fml_adr(dram_addr),
 360           .fml_din(dram_write_data),
 361           .fml_dout(dram_read_data),
 362           .fml_msk(16'h0)
 363    );
 364
 365 endmodule
 366