src/edu/berkeley/fleet/fpga/main.v

   1 //----------------------------------------------------------------------------
   2 // user_fifo_test.v
   3 //----------------------------------------------------------------------------
   4
   5 `timescale 1ps / 1ps
   6
   7 module main
   8   (
   9    // User clock ports
  10    Clkin_p,
  11    Clkin_m,
  12
  13    // SelectMAP interface ports
  14    D,                           // Data bus
  15    RDWR_B,                      // Read/write signal
  16    CS_B,                        // Chip select
  17    INIT_B,                      // Initialization/interrupt signal
  18    CCLK,                        // Local CCLK output
  19    gpleds
  20    );
  21
  22    // User clock/reset ports
  23    input                       Clkin_p;
  24    input                       Clkin_m;
  25
  26    // SelectMAP protocol ports
  27    inout [0:7]                 D;
  28    input                       RDWR_B;
  29    input                       CS_B;
  30    output                      INIT_B;
  31    output                      CCLK;
  32    output [6:1] gpleds;
  33
  34
  35    // Wires
  36    wire                        CCLK_int;
  37
  38    wire [0:31]                 LoopData;
  39    wire [0:31]                 LoopDataW;
  40    wire                        LoopEmpty;
  41    wire                        LoopFull;
  42
  43    wire [0:7]                  D_I;
  44    wire [0:7]                  D_O;
  45    wire [0:7]                  D_T;
  46
  47    wire                        User_Clk;
  48    wire                        User_Rst;
  49
  50    reg  [6:1]                  gpleds_reg;
  51
  52    // synthesis attribute tig of activate_r is yes;
  53    wire   activate_r;
  54    // synthesis attribute tig of activate_a is yes;
  55    wire   activate_a;
  56
  57    wire [7:0] write_data;
  58    wire       write_enable;
  59    wire       write_full;
  60
  61    wire [7:0] read_data;
  62    wire       read_empty;
  63    wire [7:0] read_wire;
  64
  65    reg  [7:0] write_reg;
  66    reg  [7:0] read_reg;
  67
  68    reg [7:0] read_in;
  69    wire read_enable;
  70    reg read_enable_reg;
  71    reg write_enable_reg;
  72
  73    reg root_out_a_reg;
  74    reg root_in_r_reg;
  75    reg [7:0] root_in_d_reg;
  76    wire root_in_a;
  77    wire root_in_r;
  78    wire root_out_a;
  79    wire root_out_r;
  80    wire [7:0] root_in_d;
  81
  82    root my_root(User_Clk, root_in_r, root_in_a, root_in_d,
  83                           root_out_r, root_out_a, write_data);
  84
  85    assign root_out_a = root_out_a_reg;
  86    assign root_in_r  = root_in_r_reg;
  87    assign read_enable = read_enable_reg;
  88    assign write_enable = write_enable_reg;
  89    assign root_in_d = root_in_d_reg;
  90
  91    // fpga -> host
  92    always @(posedge User_Clk)
  93    begin
  94      write_enable_reg = 0;
  95      if (root_out_r && !root_out_a_reg && !write_full) begin
  96        write_enable_reg = 1;
  97        root_out_a_reg = 1;
  98      end else if (root_out_a_reg && !root_out_r) begin
  99        root_out_a_reg = 0;
 100      end
 101      gpleds_reg[4] = write_enable_reg;
 102      gpleds_reg[5] = root_out_r;
 103      gpleds_reg[6] = root_out_a_reg;
 104    end
 105
 106    // host -> fpga
 107    always @(posedge User_Clk)
 108    begin
 109      read_enable_reg = 0;
 110      if (!read_empty && !root_in_r_reg && !root_in_a) begin
 111         root_in_r_reg = 1;
 112         root_in_d_reg = read_data;
 113         read_enable_reg = 1;
 114      end else begin
 115         if (root_in_a) begin
 116           root_in_r_reg = 0;
 117         end
 118      end
 119      gpleds_reg[1] = read_enable_reg;
 120      gpleds_reg[2] = root_in_r_reg;
 121      gpleds_reg[3] = root_in_a;
 122    end
 123
 124    assign gpleds = gpleds_reg;
 125
 126    initial
 127    begin
 128      gpleds_reg    = 0;
 129      root_in_r_reg = 0;
 130      root_in_d_reg = 0;
 131      root_out_a_reg = 0;
 132      root_in_r_reg = 0;
 133      read_enable_reg = 0;
 134      read_reg = 0;
 135      read_in = 255;
 136    end
 137
 138    // IO buffers
 139    OBUF obuf_cclk( .I( CCLK_int ),
 140                    .O( CCLK )
 141                    );
 142
 143    IOBUF iobuf_d0( .I( D_O[0] ),
 144                    .IO( D[0] ),
 145                    .O( D_I[0] ),
 146                    .T( D_T[0] )
 147                    );
 148
 149    IOBUF iobuf_d1( .I( D_O[1] ),
 150                    .IO( D[1] ),
 151                    .O( D_I[1] ),
 152                    .T( D_T[1] )
 153                    );
 154
 155    IOBUF iobuf_d2( .I( D_O[2] ),
 156                    .IO( D[2] ),
 157                    .O( D_I[2] ),
 158                    .T( D_T[2] )
 159                    );
 160
 161    IOBUF iobuf_d3( .I( D_O[3] ),
 162                    .IO( D[3] ),
 163                    .O( D_I[3] ),
 164                    .T( D_T[3] )
 165                    );
 166
 167    IOBUF iobuf_d4( .I( D_O[4] ),
 168                    .IO( D[4] ),
 169                    .O( D_I[4] ),
 170                    .T( D_T[4] )
 171                    );
 172
 173    IOBUF iobuf_d5( .I( D_O[5] ),
 174                    .IO( D[5] ),
 175                    .O( D_I[5] ),
 176                    .T( D_T[5] )
 177                    );
 178
 179    IOBUF iobuf_d6( .I( D_O[6] ),
 180                    .IO( D[6] ),
 181                    .O( D_I[6] ),
 182                    .T( D_T[6] )
 183                    );
 184
 185    IOBUF iobuf_d7( .I( D_O[7] ),
 186                    .IO( D[7] ),
 187                    .O( D_I[7] ),
 188                    .T( D_T[7] )
 189                    );
 190
 191    // Clock buffer and reset
 192    IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ),
 193                                     .IB( Clkin_m ),
 194                                     .O( User_Clk )
 195                                     );
 196
 197    wire [0:3] rst;
 198
 199    FD rst0( .D( 1'b0 ),
 200             .Q( rst[0] ),
 201             .C( User_Clk )
 202             );
 203    defparam rst0.INIT = 1'b1;
 204
 205    FD rst1( .D( rst[0] ),
 206             .Q( rst[1] ),
 207             .C( User_Clk )
 208             );
 209    defparam rst1.INIT = 1'b1;
 210
 211    FD rst2( .D( rst[1] ),
 212             .Q( rst[2] ),
 213             .C( User_Clk )
 214             );
 215    defparam rst2.INIT = 1'b1;
 216
 217    FD rst3( .D( rst[2] ),
 218             .Q( rst[3] ),
 219             .C( User_Clk )
 220             );
 221    defparam rst3.INIT = 1'b1;
 222
 223    assign   User_Rst = |rst;
 224
 225
 226    // FIFO module instantiation
 227    user_fifo test_fifo(
 228                         .WrFifo_Din( write_data ),
 229                         .WrFifo_WrEn( write_enable ),
 230                         .WrFifo_Full( write_full ),
 231                         .WrFifo_WrCnt(  ),
 232                         .RdFifo_Dout( read_data ),
 233                         .RdFifo_RdEn( read_enable ),
 234                         .RdFifo_Empty( read_empty ),
 235                         .RdFifo_RdCnt(  ),
 236                         .User_Rst( User_Rst ),
 237                         .User_Clk( User_Clk ),
 238                         .Sys_Rst( User_Rst ),
 239                         .Sys_Clk( User_Clk ),
 240                         .D_I( D_I ),
 241                         .D_O( D_O ),
 242                         .D_T( D_T ),
 243                         .RDWR_B( RDWR_B ),
 244                         .CS_B( CS_B ),
 245                         .INIT_B( INIT_B ),
 246                         .CCLK( CCLK_int )
 247                         );
 248
 249 endmodule