src/edu/berkeley/fleet/fpga/main.v

   1
   2 module main
   3  (sys_clk_pin,   /* 100Mhz */
   4   sys_rst_pin,
   5   fpga_0_RS232_Uart_1_ctsN_pin,
   6   fpga_0_RS232_Uart_1_rtsN_pin,
   7   fpga_0_RS232_Uart_1_sin_pin,
   8   fpga_0_RS232_Uart_1_sout_pin,
   9
  10   fpga_0_DDR_SDRAM_DDR_Clk_pin,
  11   fpga_0_DDR_SDRAM_DDR_Clk_n_pin,
  12   fpga_0_DDR_SDRAM_DDR_Addr_pin,
  13   fpga_0_DDR_SDRAM_DDR_BankAddr_pin,
  14   fpga_0_DDR_SDRAM_DDR_CAS_n_pin,
  15   fpga_0_DDR_SDRAM_DDR_CE_pin,
  16   fpga_0_DDR_SDRAM_DDR_CS_n_pin,
  17   fpga_0_DDR_SDRAM_DDR_RAS_n_pin,
  18   fpga_0_DDR_SDRAM_DDR_WE_n_pin,
  19   fpga_0_DDR_SDRAM_DDR_DM_pin,
  20   fpga_0_DDR_SDRAM_DDR_DQS,
  21   fpga_0_DDR_SDRAM_DDR_DQ,
  22
  23   vga_psave,
  24   vga_hsync,
  25   vga_vsync,
  26   vga_sync,
  27   vga_blank,
  28   vga_r,
  29   vga_g,
  30   vga_b,
  31   vga_clkout,
  32
  33   fpga_0_LEDs_8Bit_GPIO_IO_pin
  34  );
  35
  36   input  sys_clk_pin;
  37   input  sys_rst_pin;
  38   input  fpga_0_RS232_Uart_1_ctsN_pin;
  39   output fpga_0_RS232_Uart_1_rtsN_pin;
  40   input  fpga_0_RS232_Uart_1_sin_pin;
  41   output fpga_0_RS232_Uart_1_sout_pin;
  42
  43   output fpga_0_DDR_SDRAM_DDR_Clk_pin;
  44   output fpga_0_DDR_SDRAM_DDR_Clk_n_pin;
  45   output [12:0] fpga_0_DDR_SDRAM_DDR_Addr_pin;
  46   output [1:0] fpga_0_DDR_SDRAM_DDR_BankAddr_pin;
  47   output fpga_0_DDR_SDRAM_DDR_CAS_n_pin;
  48   output fpga_0_DDR_SDRAM_DDR_CE_pin;
  49   output fpga_0_DDR_SDRAM_DDR_CS_n_pin;
  50   output fpga_0_DDR_SDRAM_DDR_RAS_n_pin;
  51   output fpga_0_DDR_SDRAM_DDR_WE_n_pin;
  52   output [3:0] fpga_0_DDR_SDRAM_DDR_DM_pin;
  53   inout [3:0] fpga_0_DDR_SDRAM_DDR_DQS;
  54   inout [31:0] fpga_0_DDR_SDRAM_DDR_DQ;
  55
  56   wire  [31:0]  dram_addr;
  57   wire          dram_addr_r;
  58   wire          dram_addr_a;
  59   wire          dram_isread;
  60   wire  [63:0]  dram_write_data;
  61   wire          dram_write_data_push;
  62   wire          dram_write_data_full;
  63   wire   [63:0] dram_read_data;
  64   wire          dram_read_data_pop;
  65   wire          dram_read_data_empty;
  66   wire   [1:0]  dram_read_data_latency;
  67
  68   output vga_psave;
  69   output vga_hsync;
  70   output vga_vsync;
  71   output vga_sync;
  72   output vga_blank;
  73   output [7:0] vga_r;
  74   output [7:0] vga_g;
  75   output [7:0] vga_b;
  76   output vga_clkout;
  77
  78   wire clk;
  79   wire clk_fb;
  80   wire clk50mhz;
  81   wire clk_unbuffered;
  82
  83   wire vga_clk;
  84   wire vga_clk_fb;
  85   wire vga_clk_unbuffered;
  86
  87   output [7:0] fpga_0_LEDs_8Bit_GPIO_IO_pin;
  88   wire [7:0] leds;
  89   assign fpga_0_LEDs_8Bit_GPIO_IO_pin = ~leds;
  90
  91   assign leds[5:0] = dram_read_data[5:0];
  92   assign leds[6] = dram_addr_r;
  93   assign leds[7] = dram_addr_a;
  94
  95
  96   //assign clk = sys_clk_pin;
  97 /*
  98   reg clk_unbuffered;
  99   initial clk_unbuffered = 0;
 100
 101   always @(posedge sys_clk_pin) begin
 102     clk_unbuffered = ~clk_unbuffered;
 103   end
 104
 105   assign clk_unbuffered = sys_clk_pin;
 106 */
 107   BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));
 108
 109   DCM
 110    #(
 111       .CLKFX_MULTIPLY(4),
 112       .CLKFX_DIVIDE(8),
 113       .CLKIN_PERIOD("10 ns")
 114     ) mydcm(
 115       .CLKIN (sys_clk_pin),
 116       .CLKFB(clk_fb),
 117       .CLKFX (clk_unbuffered),
 118       .CLK0  (clk_fb)
 119     );
 120
 121   BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
 122   DCM  // 25Mhz VGA clock
 123    #(
 124       .CLKFX_MULTIPLY(4),
 125       .CLKFX_DIVIDE(16),
 126       .CLKIN_PERIOD("20 ns")
 127     ) vgadcm (
 128       .CLKIN (clk_unbuffered),
 129       .CLKFB(vga_clk_fb),
 130       .CLKFX (vga_clk_unbuffered),
 131       .CLK0  (vga_clk_fb)
 132     );
 133
 134
 135   wire break_o;
 136   wire break;
 137   reg break_last;
 138   reg send_k;                initial send_k = 0;
 139   wire rst;
 140   assign rst = sys_rst_pin;
 141
 142   wire       data_to_host_full;
 143   wire       data_to_host_write_enable;
 144   wire [7:0] data_to_host;
 145
 146   wire       data_to_fleet_empty;
 147   wire       data_to_fleet_read_enable;
 148   wire [7:0] data_to_fleet;
 149
 150   reg we;
 151   reg re;
 152   reg [7:0] data_to_host_r;
 153   assign data_to_host = data_to_host_r;
 154
 155   wire ser_rst;
 156   reg ser_rst_r;
 157   initial ser_rst_r = 0;
 158   assign ser_rst = (rst & ser_rst_r);
 159
 160   wire sio_ce;
 161   wire sio_ce_x4;
 162   //sasc_brg sasc_brg(clk, ser_rst, 8, 65, sio_ce, sio_ce_x4);
 163   //  sasc_brg sasc_brg(clk, ser_rst, 3, 65, sio_ce, sio_ce_x4);
 164   sasc_brg sasc_brg(sys_clk_pin, ser_rst, 8, 65, sio_ce, sio_ce_x4);
 165   sasc_top sasc_top(clk, ser_rst,
 166                     fpga_0_RS232_Uart_1_sin_pin,
 167                     fpga_0_RS232_Uart_1_sout_pin,
 168                     fpga_0_RS232_Uart_1_ctsN_pin,
 169                     fpga_0_RS232_Uart_1_rtsN_pin,
 170                     sio_ce,
 171                     sio_ce_x4,
 172                     data_to_host,
 173                     data_to_fleet,
 174                     data_to_fleet_read_enable,
 175                     data_to_host_write_enable,
 176                     data_to_host_full,
 177                     data_to_fleet_empty,
 178                     break_o,
 179                     break);
 180
 181    // break and break_o are _active high_
 182    always @(posedge clk) break_last <= break_o;
 183    assign break      =  break_o && !break_last;
 184    assign break_done = !break_o &&  break_last;
 185
 186    reg data_to_host_write_enable_reg;
 187    reg data_to_fleet_read_enable_reg;
 188
 189    reg root_out_a_reg;
 190    reg root_in_r_reg;
 191    reg [7:0] root_in_d_reg;
 192    wire root_in_a;
 193    wire root_in_r;
 194    wire root_out_a;
 195    wire root_out_r;
 196    wire [7:0] root_in_d;
 197    wire [7:0] root_out_d;
 198
 199    /*
 200     * There is some very weird timing thing going on here; we need to
 201     * hold reset low for more than one clock in order for it to propagate
 202     * all the way to the docks.
 203     */
 204    root my_root(clk, rst && !break_o,
 205                 root_in_r,  root_in_a,  root_in_d,
 206                 root_out_r, root_out_a, root_out_d,
 207                 dram_addr,
 208                 dram_addr_r,
 209                 dram_addr_a,
 210                 dram_isread,
 211                 dram_write_data,
 212                 dram_write_data_push,
 213                 dram_write_data_full,
 214                 dram_read_data,
 215                 dram_read_data_pop,
 216                 dram_read_data_empty,
 217                 dram_read_data_latency,
 218                 vga_clk,
 219                 vga_psave,
 220                 vga_hsync,
 221                 vga_vsync,
 222                 vga_sync,
 223                 vga_blank,
 224                 vga_r,
 225                 vga_g,
 226                 vga_b,
 227                 vga_clkout
 228                );
 229 /*
 230    fifo4 my_root(clk, rst,
 231                 root_in_r,  root_in_a,  root_in_d,
 232                 root_out_r, root_out_a, data_to_host);
 233 */
 234    assign root_out_a                = root_out_a_reg;
 235    assign root_in_r                 = root_in_r_reg;
 236    assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
 237    assign data_to_host_write_enable = data_to_host_write_enable_reg;
 238    assign root_in_d                 = root_in_d_reg;
 239
 240    // fpga -> host
 241    always @(posedge clk)
 242    begin
 243      if (break) begin
 244        root_out_a_reg = 0;
 245        data_to_host_write_enable_reg <= 0;
 246
 247      end else if (break_done) begin
 248        data_to_host_write_enable_reg <= 1;
 249        data_to_host_r <= 111;
 250        send_k <= 1;
 251      end else if (send_k) begin
 252        data_to_host_write_enable_reg <= 1;
 253        data_to_host_r <= 107;
 254        send_k <= 0;
 255
 256
 257      end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
 258        data_to_host_write_enable_reg <= 1;
 259        data_to_host_r <= root_out_d;
 260        root_out_a_reg = 1;
 261      end else if (root_out_a_reg && !root_out_r) begin
 262        data_to_host_write_enable_reg <= 0;
 263        root_out_a_reg = 0;
 264      end else begin
 265        data_to_host_write_enable_reg <= 0;
 266      end
 267    end
 268
 269    // host -> fpga
 270    always @(posedge clk)
 271    begin
 272      ser_rst_r <= 1;
 273      if (break) begin
 274        root_in_r_reg <= 0;
 275        root_in_d_reg <= 0;
 276        data_to_fleet_read_enable_reg <= 0;
 277      end else
 278
 279      if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
 280         root_in_r_reg <= 1;
 281         root_in_d_reg <= data_to_fleet;
 282         data_to_fleet_read_enable_reg <= 1;
 283      end else begin
 284        data_to_fleet_read_enable_reg <= 0;
 285         if (root_in_a) begin
 286           root_in_r_reg <= 0;
 287         end
 288      end
 289    end
 290
 291    initial
 292    begin
 293      root_in_r_reg = 0;
 294      root_in_d_reg = 0;
 295      root_out_a_reg = 0;
 296      data_to_fleet_read_enable_reg = 0;
 297      data_to_host_write_enable_reg = 0;
 298    end
 299
 300    ddr_ctrl
 301    #(
 302         .clk_freq( 50000000 ),
 303         .clk_multiply( 12 ),
 304         .clk_divide( 5 ),
 305         .phase_shift( 0 ),
 306         .wait200_init( 26 )
 307    ) ddr_ctrl (
 308           .ddr_a( fpga_0_DDR_SDRAM_DDR_Addr_pin ),
 309           .ddr_clk( fpga_0_DDR_SDRAM_DDR_Clk_pin ),
 310           .ddr_clk_n( fpga_0_DDR_SDRAM_DDR_Clk_n_pin ),
 311           .ddr_ba( fpga_0_DDR_SDRAM_DDR_BankAddr_pin ),
 312           .ddr_dq( fpga_0_DDR_SDRAM_DDR_DQ ),
 313           .ddr_dm( fpga_0_DDR_SDRAM_DDR_DM_pin ),
 314           .ddr_dqs( fpga_0_DDR_SDRAM_DDR_DQS ),
 315           .ddr_cs_n( fpga_0_DDR_SDRAM_DDR_CS_n_pin ),
 316           .ddr_ras_n( fpga_0_DDR_SDRAM_DDR_RAS_n_pin ),
 317           .ddr_cas_n( fpga_0_DDR_SDRAM_DDR_CAS_n_pin ),
 318           .ddr_we_n( fpga_0_DDR_SDRAM_DDR_WE_n_pin ),
 319           .ddr_cke( fpga_0_DDR_SDRAM_DDR_CE_pin ),
 320
 321           .clk(clk),
 322           .reset(!rst),
 323           .rot(3'b011),
 324
 325           .fml_wr(!dram_isread && dram_addr_r),
 326           .fml_done(dram_addr_a),
 327           .fml_rd( dram_isread && dram_addr_r),
 328           .fml_adr(dram_addr),
 329           .fml_din(dram_write_data),
 330           .fml_dout(dram_read_data),
 331 //          .fml_msk(16'hffff)
 332           .fml_msk(16'h0)
 333    );
 334
 335 endmodule
 336