src/edu/berkeley/fleet/fpga/main.v

   1
   2 module main
   3  (sys_clk_pin,   /* I think this is 100Mhz */
   4   sys_rst_pin,
   5   fpga_0_RS232_Uart_1_ctsN_pin,
   6   fpga_0_RS232_Uart_1_rtsN_pin,
   7   fpga_0_RS232_Uart_1_sin_pin,
   8   fpga_0_RS232_Uart_1_sout_pin
   9  );
  10
  11   input  sys_clk_pin;
  12   input  sys_rst_pin;
  13   input  fpga_0_RS232_Uart_1_ctsN_pin;
  14   output fpga_0_RS232_Uart_1_rtsN_pin;
  15   input  fpga_0_RS232_Uart_1_sin_pin;
  16   output fpga_0_RS232_Uart_1_sout_pin;
  17
  18   wire clk;
  19   assign clk = sys_clk_pin;
  20   wire break;
  21   wire rst;
  22   assign rst = sys_rst_pin;
  23
  24   wire       data_to_host_full;
  25   wire       data_to_host_write_enable;
  26   wire [7:0] data_to_host;
  27
  28   wire       data_to_fleet_empty;
  29   wire       data_to_fleet_read_enable;
  30   wire [7:0] data_to_fleet;
  31
  32   reg we;
  33   reg re;
  34   reg [7:0] data_to_host_r;
  35
  36   wire ser_rst;
  37   reg ser_rst_r;
  38   initial ser_rst_r = 0;
  39   assign ser_rst = rst & ser_rst_r;
  40
  41   wire sio_ce;
  42   wire sio_ce_x4;
  43   sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
  44   sasc_top sasc_top(clk, ser_rst,
  45                     fpga_0_RS232_Uart_1_sin_pin,
  46                     fpga_0_RS232_Uart_1_sout_pin,
  47                     fpga_0_RS232_Uart_1_ctsN_pin,
  48                     fpga_0_RS232_Uart_1_rtsN_pin,
  49                     sio_ce,
  50                     sio_ce_x4,
  51                     data_to_host,
  52                     data_to_fleet,
  53                     data_to_fleet_read_enable,
  54                     data_to_host_write_enable,
  55                     data_to_host_full,
  56                     data_to_fleet_empty,
  57                     break);
  58
  59    reg data_to_host_write_enable_reg;
  60    reg data_to_fleet_read_enable_reg;
  61
  62    reg root_out_a_reg;
  63    reg root_in_r_reg;
  64    reg [7:0] root_in_d_reg;
  65    wire root_in_a;
  66    wire root_in_r;
  67    wire root_out_a;
  68    wire root_out_r;
  69    wire [7:0] root_in_d;
  70
  71
  72    root my_root(clk, rst && !break,
  73                 root_in_r,  root_in_a,  root_in_d,
  74                 root_out_r, root_out_a, data_to_host);
  75 /*
  76    fifo4 my_root(clk, rst,
  77                 root_in_r,  root_in_a,  root_in_d,
  78                 root_out_r, root_out_a, data_to_host);
  79 */
  80    assign root_out_a                = root_out_a_reg;
  81    assign root_in_r                 = root_in_r_reg;
  82    assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
  83    assign data_to_host_write_enable = data_to_host_write_enable_reg;
  84    assign root_in_d                 = root_in_d_reg;
  85
  86    // fpga -> host
  87    always @(posedge clk)
  88    begin
  89      data_to_host_write_enable_reg = 0;
  90      if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
  91        data_to_host_write_enable_reg = 1;
  92        root_out_a_reg = 1;
  93      end else if (root_out_a_reg && !root_out_r) begin
  94        root_out_a_reg = 0;
  95      end
  96    end
  97
  98    // host -> fpga
  99    always @(posedge clk)
 100    begin
 101      ser_rst_r <= 1;
 102      data_to_fleet_read_enable_reg = 0;
 103      if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
 104         root_in_r_reg = 1;
 105         root_in_d_reg = data_to_fleet;
 106         data_to_fleet_read_enable_reg = 1;
 107      end else begin
 108         if (root_in_a) begin
 109           root_in_r_reg = 0;
 110         end
 111      end
 112    end
 113
 114    initial
 115    begin
 116      root_in_r_reg = 0;
 117      root_in_d_reg = 0;
 118      root_out_a_reg = 0;
 119      data_to_fleet_read_enable_reg = 0;
 120      data_to_host_write_enable_reg = 0;
 121    end
 122 endmodule
 123
 124