src/edu/berkeley/fleet/fpga/main.v

   1
   2 module main
   3  (sys_clk_pin,   /* I think this is 100Mhz */
   4   sys_rst_pin,
   5   fpga_0_RS232_Uart_1_ctsN_pin,
   6   fpga_0_RS232_Uart_1_rtsN_pin,
   7   fpga_0_RS232_Uart_1_sin_pin,
   8   fpga_0_RS232_Uart_1_sout_pin
   9  );
  10
  11   input  sys_clk_pin;
  12   input  sys_rst_pin;
  13   input  fpga_0_RS232_Uart_1_ctsN_pin;
  14   output fpga_0_RS232_Uart_1_rtsN_pin;
  15   input  fpga_0_RS232_Uart_1_sin_pin;
  16   output fpga_0_RS232_Uart_1_sout_pin;
  17
  18   wire clk;
  19   assign clk = sys_clk_pin;
  20   wire rst;
  21   assign rst = sys_rst_pin;
  22
  23   wire       data_to_host_full;
  24   wire       data_to_host_write_enable;
  25   wire [7:0] data_to_host;
  26
  27   wire       data_to_fleet_empty;
  28   wire       data_to_fleet_read_enable;
  29   wire [7:0] data_to_fleet;
  30
  31   reg we;
  32   reg re;
  33   reg [7:0] data_to_host_r;
  34
  35 /*
  36   assign data_to_host              = data_to_host_r;
  37   assign data_to_host_write_enable = we;
  38   assign data_to_fleet_read_enable = re;
  39
  40   reg [7:0] count;
  41   initial count = 0;
  42   initial we = 0;
  43   initial re = 0;
  44   initial data_to_host_r = 107;
  45   always @(posedge clk) begin
  46     if (re && !data_to_fleet_empty) begin
  47       data_to_host_r <= data_to_fleet;
  48       we <= 1;
  49     end else begin
  50       we <= 0;
  51     end
  52     if (data_to_host_full || data_to_fleet_empty) begin
  53       re <= 0;
  54     end else begin
  55       re <= 1;
  56     end
  57   end
  58 */
  59
  60   wire ser_rst;
  61   reg ser_rst_r;
  62   initial ser_rst_r = 0;
  63   assign ser_rst = rst & ser_rst_r;
  64    wire break;
  65
  66   wire sio_ce;
  67   wire sio_ce_x4;
  68   sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
  69   sasc_top sasc_top(clk, ser_rst,
  70                     fpga_0_RS232_Uart_1_sin_pin,
  71                     fpga_0_RS232_Uart_1_sout_pin,
  72                     fpga_0_RS232_Uart_1_ctsN_pin,
  73                     fpga_0_RS232_Uart_1_rtsN_pin,
  74                     sio_ce,
  75                     sio_ce_x4,
  76                     data_to_host,
  77                     data_to_fleet,
  78                     data_to_fleet_read_enable,
  79                     data_to_host_write_enable,
  80                     data_to_host_full,
  81                     data_to_fleet_empty,
  82                     break);
  83
  84    reg data_to_host_write_enable_reg;
  85    reg data_to_fleet_read_enable_reg;
  86
  87    reg root_out_a_reg;
  88    reg root_in_r_reg;
  89    reg [7:0] root_in_d_reg;
  90    wire root_in_a;
  91    wire root_in_r;
  92    wire root_out_a;
  93    wire root_out_r;
  94    wire [7:0] root_in_d;
  95
  96    root my_root(clk, rst,
  97                 root_in_r,  root_in_a,  root_in_d,
  98                 root_out_r, root_out_a, data_to_host);
  99 /*
 100    fifo4 my_root(clk, rst,
 101                 root_in_r,  root_in_a,  root_in_d,
 102                 root_out_r, root_out_a, data_to_host);
 103 */
 104    assign root_out_a                = root_out_a_reg;
 105    assign root_in_r                 = root_in_r_reg;
 106    assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
 107    assign data_to_host_write_enable = data_to_host_write_enable_reg;
 108    assign root_in_d                 = root_in_d_reg;
 109
 110    // fpga -> host
 111    always @(posedge clk)
 112    begin
 113      data_to_host_write_enable_reg = 0;
 114      if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
 115        data_to_host_write_enable_reg = 1;
 116        root_out_a_reg = 1;
 117      end else if (root_out_a_reg && !root_out_r) begin
 118        root_out_a_reg = 0;
 119      end
 120    end
 121
 122    // awful hack to flush the superfluous null byte that seems to appear on bootup
 123    reg [15:0] boot_counter;
 124
 125    // host -> fpga
 126    always @(posedge clk)
 127    begin
 128      ser_rst_r <= 1;
 129 /*
 130      if (boot_counter != 500) begin
 131        data_to_fleet_read_enable_reg = 1;
 132        if (sio_ce) begin
 133          boot_counter <= boot_counter + 1;
 134        end
 135      end else begin
 136 */
 137        data_to_fleet_read_enable_reg = 0;
 138 /*
 139        if (break) begin
 140           root_in_d_reg = 98;
 141           root_in_r_reg = 1;
 142        end else
 143 */
 144        if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
 145           root_in_r_reg = 1;
 146           root_in_d_reg = data_to_fleet;
 147           data_to_fleet_read_enable_reg = 1;
 148        end else begin
 149           if (root_in_a) begin
 150             root_in_r_reg = 0;
 151           end
 152        end
 153 /*
 154      end
 155 */
 156    end
 157
 158    initial
 159    begin
 160      boot_counter = 0;
 161      root_in_r_reg = 0;
 162      root_in_d_reg = 0;
 163      root_out_a_reg = 0;
 164      data_to_fleet_read_enable_reg = 0;
 165      data_to_host_write_enable_reg = 0;
 166    end
 167 endmodule
 168
 169