src/edu/berkeley/fleet/fpga/mem/sasc_fifo4.v

   1 /////////////////////////////////////////////////////////////////////
   2 ////                                                             ////
   3 ////  FIFO 4 entries deep                                        ////
   4 ////                                                             ////
   5 ////                                                             ////
   6 ////  Author: Rudolf Usselmann                                   ////
   7 ////          rudi@asics.ws                                      ////
   8 ////                                                             ////
   9 ////                                                             ////
  10 ////  Downloaded from: http://www.opencores.org/cores/sasc/      ////
  11 ////                                                             ////
  12 /////////////////////////////////////////////////////////////////////
  13 ////                                                             ////
  14 //// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
  15 ////                         www.asics.ws                        ////
  16 ////                         rudi@asics.ws                       ////
  17 ////                                                             ////
  18 //// This source file may be used and distributed without        ////
  19 //// restriction provided that this copyright statement is not   ////
  20 //// removed from the file and that any derivative work contains ////
  21 //// the original copyright notice and the associated disclaimer.////
  22 ////                                                             ////
  23 ////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
  24 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
  25 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
  26 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
  27 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
  28 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
  29 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
  30 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
  31 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
  32 //// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
  33 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
  34 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
  35 //// POSSIBILITY OF SUCH DAMAGE.                                 ////
  36 ////                                                             ////
  37 /////////////////////////////////////////////////////////////////////
  38
  39 //  CVS Log
  40 //
  41 //  $Id: sasc_fifo4.v,v 1.1.1.1 2002/09/16 16:16:41 rudi Exp $
  42 //
  43 //  $Date: 2002/09/16 16:16:41 $
  44 //  $Revision: 1.1.1.1 $
  45 //  $Author: rudi $
  46 //  $Locker:  $
  47 //  $State: Exp $
  48 //
  49 // Change History:
  50 //               $Log: sasc_fifo4.v,v $
  51 //               Revision 1.1.1.1  2002/09/16 16:16:41  rudi
  52 //               Initial Checkin
  53 //
  54 //
  55 //
  56 //
  57 //
  58 //
  59
  60 `include "timescale.v"
  61
  62 // 4 entry deep fast fifo
  63 module sasc_fifo4(clk, rst, clr,  din, we, dout, re, full, empty);
  64
  65 input           clk, rst;
  66 input           clr;
  67 input   [7:0]   din;
  68 input           we;
  69 output  [7:0]   dout;
  70 input           re;
  71 output          full, empty;
  72
  73 ////////////////////////////////////////////////////////////////////
  74 //
  75 // Local Wires
  76 //
  77
  78 reg     [7:0]   mem[0:3];
  79 reg     [1:0]   wp;
  80 reg     [1:0]   rp;
  81 wire    [1:0]   wp_p1;
  82 wire    [1:0]   wp_p2;
  83 wire    [1:0]   rp_p1;
  84 wire            full, empty;
  85 reg             gb;
  86
  87 initial wp = 0;
  88 initial rp = 0;
  89 initial gb = 0;
  90
  91 ////////////////////////////////////////////////////////////////////
  92 //
  93 // Misc Logic
  94 //
  95
  96 always @(posedge clk or negedge rst)
  97         if(!rst)        wp <= #1 2'h0;
  98         else
  99         if(clr)         wp <= #1 2'h0;
 100         else
 101         if(we)          wp <= #1 wp_p1;
 102
 103 assign wp_p1 = wp + 2'h1;
 104 assign wp_p2 = wp + 2'h2;
 105
 106 always @(posedge clk or negedge rst)
 107         if(!rst)        rp <= #1 2'h0;
 108         else
 109         if(clr)         rp <= #1 2'h0;
 110         else
 111         if(re)          rp <= #1 rp_p1;
 112
 113 assign rp_p1 = rp + 2'h1;
 114
 115 // Fifo Output
 116 assign  dout = mem[ rp ];
 117
 118 // Fifo Input
 119 always @(posedge clk)
 120         if(we)     mem[ wp ] <= #1 din;
 121
 122 // Status
 123 assign empty = (wp == rp) & !gb;
 124 assign full  = (wp == rp) &  gb;
 125
 126 // Guard Bit ...
 127 always @(posedge clk)
 128         if(!rst)                        gb <= #1 1'b0;
 129         else
 130         if(clr)                         gb <= #1 1'b0;
 131         else
 132         if((wp_p1 == rp) & we)          gb <= #1 1'b1;
 133         else
 134         if(re)                          gb <= #1 1'b0;
 135
 136 endmodule
 137
 138