1 /////////////////////////////////////////////////////////////////////
3 //// Simple Asynchronous Serial Comm. Device ////
6 //// Author: Rudolf Usselmann ////
7 //// rudi@asics.ws ////
10 //// Downloaded from: http://www.opencores.org/cores/sasc/ ////
12 /////////////////////////////////////////////////////////////////////
14 //// Copyright (C) 2000-2002 Rudolf Usselmann ////
15 //// www.asics.ws ////
16 //// rudi@asics.ws ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer.////
23 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
25 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
26 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
27 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
28 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
29 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
30 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
31 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
32 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
33 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
34 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
35 //// POSSIBILITY OF SUCH DAMAGE. ////
37 /////////////////////////////////////////////////////////////////////
41 // $Id: sasc_top.v,v 1.2 2006/03/30 02:47:07 rudi Exp $
43 // $Date: 2006/03/30 02:47:07 $
50 // $Log: sasc_top.v,v $
51 // Revision 1.2 2006/03/30 02:47:07 rudi
52 // Thanks to Darren O'Connor of SPEC, Inc. for fixing a bug
53 // with the DPLL and data alignment:
55 // You were right that it was a problem with the dpll. I found
56 // that it was possible to get two baud clocks (rx_sio_ce) during
57 // one bit period. I fixed the problem by delaying the input data
58 // signal with a shift register and using that in the equations
59 // for the "change" variable that controls the DPLL FSM.
61 // Revision 1.1.1.1 2002/09/16 16:16:42 rudi
72 `include "timescale.v"
76 ===============================
83 module sasc_top( clk, rst,
86 rxd_i, txd_o, cts_i, rts_o,
88 // External Baud Rate Generator
92 din_i, dout_o, re_i, we_i, full_o, empty_o,
109 output full_o, empty_o;
111 ///////////////////////////////////////////////////////////////////
113 // Local Wires and Registers
116 parameter START_BIT = 1'b0,
128 reg [3:0] tx_bit_cnt;
131 reg [3:0] rx_bit_cnt;
134 reg rx_valid, rx_valid_r;
143 reg rx_sio_ce_d, rx_sio_ce_r1, rx_sio_ce_r2, rx_sio_ce;
144 reg [1:0] dpll_state, dpll_next_state;
145 reg [5:0] rxd_dly; //New input delay used to ensure no baud clocks
146 // occur twice in one baud period
147 ///////////////////////////////////////////////////////////////////
152 sasc_fifo4 tx_fifo( .clk( clk ),
153 .rst( rst && !flush_i ),
163 sasc_fifo4 rx_fifo( .clk( clk ),
164 .rst( rst && !flush_i ),
174 ///////////////////////////////////////////////////////////////////
178 always @(posedge clk)
179 if(!rst) txf_empty_r <= #1 1'b1;
181 if(sio_ce) txf_empty_r <= #1 txf_empty;
183 always @(posedge clk)
184 load <= #1 !txf_empty_r & !shift_en & !cts_i;
186 always @(posedge clk)
189 assign load_e = load & sio_ce;
191 always @(posedge clk)
192 if(load_e) hold_reg <= #1 {STOP_BIT, txd_p, START_BIT};
194 if(shift_en & sio_ce) hold_reg <= #1 {IDLE_BIT, hold_reg[9:1]};
196 always @(posedge clk)
197 if(!rst) txd_o <= #1 IDLE_BIT;
200 if(shift_en | shift_en_r) txd_o <= #1 hold_reg[0];
201 else txd_o <= #1 IDLE_BIT;
203 always @(posedge clk)
204 if(!rst) tx_bit_cnt <= #1 4'h9;
206 if(load_e) tx_bit_cnt <= #1 4'h0;
208 if(shift_en & sio_ce) tx_bit_cnt <= #1 tx_bit_cnt + 4'h1;
210 always @(posedge clk)
211 shift_en <= #1 (tx_bit_cnt != 4'h9);
213 always @(posedge clk)
214 if(!rst) shift_en_r <= #1 1'b0;
216 if(sio_ce) shift_en_r <= #1 shift_en;
218 ///////////////////////////////////////////////////////////////////
223 always @(posedge clk)
225 rxd_dly[5:1] <= #1 rxd_dly[4:0];
226 rxd_dly[0] <= #1rxd_i;
227 rxd_s <= #1rxd_dly[5]; // rxd_s = delay 1
228 rxd_r <= #1 rxd_s; // rxd_r = delay 2
232 assign start = (rxd_r == IDLE_BIT) & (rxd_s == START_BIT);
234 always @(posedge clk)
235 if(!rst) rx_bit_cnt <= #1 4'ha;
237 if(!rx_go & start) rx_bit_cnt <= #1 4'h0;
239 if(rx_go & rx_sio_ce) rx_bit_cnt <= #1 rx_bit_cnt + 4'h1;
241 always @(posedge clk)
242 rx_go <= #1 (rx_bit_cnt != 4'ha);
244 assign break_o = break_r;
245 always @(posedge clk)
246 rx_valid <= #1 (rx_bit_cnt == 4'h9) && (rxd_s == STOP_BIT);
247 always @(posedge clk)
248 break_r <= #1 (rx_bit_cnt == 4'h9) && (rxr[9:0]==10'b0) && (rxd_dly == 5'b0) && (rxd_s == 0) && (rxd_r == 0);
250 always @(posedge clk)
251 rx_valid_r <= #1 rx_valid;
253 assign rx_we = !rx_valid_r & rx_valid & !rxf_full;
255 always @(posedge clk)
256 if(rx_go & rx_sio_ce) rxr <= {rxd_s, rxr[9:1]};
258 always @(posedge clk)
259 rts_o <= #1 rxf_full;
261 ///////////////////////////////////////////////////////////////////
266 // Uses 4x baud clock to lock to incoming stream
269 always @(posedge clk)
270 if(sio_ce_x4) rxd_r1 <= #1 rxd_s;
272 always @(posedge clk)
273 if(sio_ce_x4) rxd_r2 <= #1 rxd_r1;
275 always @(posedge clk)
278 else if ((rxd_dly[1] != rxd_r1) || (rxd_dly[1] != rxd_s))
284 always @(posedge clk or negedge rst)
285 if(!rst) dpll_state <= #1 2'h1;
287 if(sio_ce_x4) dpll_state <= #1 dpll_next_state;
289 always @(dpll_state or change)
294 if(change) dpll_next_state = 3'h0;
295 else dpll_next_state = 3'h1;
298 if(change) dpll_next_state = 3'h3;
299 else dpll_next_state = 3'h2;
302 if(change) dpll_next_state = 3'h0;
303 else dpll_next_state = 3'h3;
305 if(change) dpll_next_state = 3'h0;
306 else dpll_next_state = 3'h0;
310 // Compensate for sync registers at the input - allign sio
311 // clock enable to be in the middle between two bit changes ...
312 always @(posedge clk)
313 rx_sio_ce_r1 <= #1 rx_sio_ce_d;
315 always @(posedge clk)
316 rx_sio_ce_r2 <= #1 rx_sio_ce_r1;
318 always @(posedge clk)
319 rx_sio_ce <= #1 rx_sio_ce_r1 & !rx_sio_ce_r2;