src/edu/berkeley/fleet/fpga/ramfifo.inc

   1 module `MODULE_NAME(clk, rst,
   2                in_r, in_a_, in_d,
   3                out_r_, out_a, out_d_);
   4     input  clk;
   5     input  rst;
   6     input  in_r;
   7     output in_a_;
   8     output out_r_;
   9     input  out_a;
  10     input  [(`WIDTH-1):0] in_d;
  11     output [(`WIDTH-1):0] out_d_;
  12
  13     reg in_a;
  14     reg out_r;
  15     assign in_a_ = in_a;
  16     assign out_r_ = out_r;
  17
  18     wire[((1<<(`ADDR_BITS))-1):0] controlx;
  19     reg[((1<<(`ADDR_BITS))-1):0] control;
  20     initial control = 0;
  21
  22     genvar i;
  23     generate
  24       if (`ADDR_BITS > 1) begin: OUT
  25       for(i=1; i<=((1<<`ADDR_BITS)-2) ; i=i+1) begin : OUT
  26         assign controlx[i] =
  27            ( control[i-1] && !control[i]                 ) ? 1 :
  28            (                  control[i] && !control[i+1]) ? 0 :
  29            control[i];
  30       end
  31       end
  32     endgenerate
  33
  34     reg[3:0] addr;
  35     initial  addr = 4'b1111;
  36
  37     genvar j;
  38     generate
  39       for(j=0; j<`WIDTH ; j=j+1) begin : OUTX
  40          SRL16E SRL16E (.Q (out_d_[j]),
  41                         .A0 (addr[0]),
  42                         .A1 (addr[1]),
  43                         .A2 (addr[2]),
  44                         .A3 (addr[3]),
  45                         .CE (in_r && !in_a && !control[0]),
  46                         .CLK (clk),
  47                         .D (in_d[j]));
  48          defparam SRL16E.INIT = 0;
  49       end
  50     endgenerate
  51
  52     assign controlx[(1<<`ADDR_BITS)-1] =
  53         !control[(1<<`ADDR_BITS)-1] ? control[(1<<`ADDR_BITS)-2] : (!out_r && !out_a) ? 0 : control[(1<<`ADDR_BITS)-1];
  54
  55     reg inchead;
  56     reg inctail;
  57
  58     always @(posedge clk) begin
  59         if (!rst) begin
  60           out_r <= 0;
  61           in_a <= 0;
  62           control <= 0;
  63           addr <= 4'b1111;
  64         end else begin
  65           inchead = 0;
  66           inctail = 0;
  67           if (!in_r && in_a) in_a <= 0;
  68           if (control[0]) begin
  69              if (!control[1]) control[0] <= 0;
  70           end else if (in_r && !in_a) begin
  71             control[0] <= 1;
  72             inctail = 1;
  73             in_a <= 1;
  74           end
  75
  76           control[(1<<`ADDR_BITS)-1:1] <= controlx[(1<<`ADDR_BITS)-1:1];
  77
  78           if (control[(1<<`ADDR_BITS)-1] && !out_r && !out_a) begin
  79             out_r <= 1;
  80           end
  81           if (out_r && out_a) begin
  82             out_r <= 0;
  83             inchead = 1;
  84           end
  85           if (          inchead && !inctail) begin
  86             addr <= addr-1;
  87           end else if (!inchead &&  inctail) begin
  88             addr <= addr+1;
  89           end
  90       end
  91     end
  92 endmodule