src/edu/berkeley/fleet/fpga/root.v

   1 `include "macros.v"
   2
   3 module root(clk, in_r,   in_a_, in_d,
   4                  out_r_, out_a, out_d_);
   5
   6   input        clk;
   7
   8   `input(in_r,   in_a, in_a_,    [7:0], in_d)
   9   `output(out_r, out_r_, out_a,  [7:0], out_d_)
  10
  11   `defreg(horn_in_r_, [0:0],          horn_in_r)
  12   `defreg(horn_in_d_, [(`PACKET_WIDTH-1):0], horn_in_d)
  13   `defreg(funnel_out_a_, [0:0],       funnel_out_a)
  14
  15   reg [(`DATAWIDTH-1):0] out_d;
  16   assign out_d_ = out_d[7:0];
  17
  18   reg [7:0]          count_in;
  19   reg [7:0]          count_out;
  20   reg                full_in;
  21   reg                full_out;
  22
  23   initial full_in   = 0;
  24   initial count_in  = 0;
  25   initial full_out  = 0;
  26   initial count_out = 0;
  27
  28   wire [(`DATAWIDTH-1):0] funnel_out_d;
  29   fabric fabric(clk, horn_in_r_,   horn_in_a,     horn_in_d_,
  30                      funnel_out_r, funnel_out_a_, funnel_out_d);
  31
  32   // host -> fpga
  33   always @(posedge clk) begin
  34     if (!full_in) begin
  35       `onread(in_r, in_a)
  36           horn_in_d = (horn_in_d << 8) | in_d;
  37           count_in = count_in + 1;
  38           if (count_in >= 6) full_in = 1;
  39       end
  40     end else begin
  41       if (full_in) begin
  42         `onwrite(horn_in_r, horn_in_a)
  43           full_in = 0;
  44           count_in = 0;
  45         end
  46       end
  47     end
  48   end
  49
  50   // fpga -> host
  51   always @(posedge clk) begin
  52     if (!full_out) begin
  53       `onread(funnel_out_r, funnel_out_a)
  54           full_out = 1;
  55           count_out = 6;
  56           out_d = funnel_out_d;
  57       end
  58     end else begin
  59       `onwrite(out_r, out_a)
  60         out_d = out_d >> 8;
  61         count_out = count_out - 1;
  62         if (count_out==0) full_out = 0;
  63       end
  64     end
  65   end
  66
  67 endmodule