1 /////////////////////////////////////////////////////////////////////
3 //// FIFO 4 entries deep ////
6 //// Author: Rudolf Usselmann ////
7 //// rudi@asics.ws ////
10 //// Downloaded from: http://www.opencores.org/cores/sasc/ ////
12 /////////////////////////////////////////////////////////////////////
14 //// Copyright (C) 2000-2002 Rudolf Usselmann ////
15 //// www.asics.ws ////
16 //// rudi@asics.ws ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer.////
23 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
25 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
26 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
27 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
28 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
29 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
30 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
31 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
32 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
33 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
34 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
35 //// POSSIBILITY OF SUCH DAMAGE. ////
37 /////////////////////////////////////////////////////////////////////
41 // $Id: sasc_fifo4.v,v 1.1.1.1 2002/09/16 16:16:41 rudi Exp $
43 // $Date: 2002/09/16 16:16:41 $
44 // $Revision: 1.1.1.1 $
50 // $Log: sasc_fifo4.v,v $
51 // Revision 1.1.1.1 2002/09/16 16:16:41 rudi
60 `include "timescale.v"
62 // 4 entry deep fast fifo
63 module sasc_fifo4(clk, rst, clr, din, we, dout, re, full, empty);
73 ////////////////////////////////////////////////////////////////////
91 ////////////////////////////////////////////////////////////////////
96 always @(posedge clk or negedge rst)
97 if(!rst) wp <= #1 2'h0;
99 if(clr) wp <= #1 2'h0;
101 if(we) wp <= #1 wp_p1;
103 assign wp_p1 = wp + 2'h1;
104 assign wp_p2 = wp + 2'h2;
106 always @(posedge clk or negedge rst)
107 if(!rst) rp <= #1 2'h0;
109 if(clr) rp <= #1 2'h0;
111 if(re) rp <= #1 rp_p1;
113 assign rp_p1 = rp + 2'h1;
116 assign dout = mem[ rp ];
119 always @(posedge clk)
120 if(we) mem[ wp ] <= #1 din;
123 assign empty = (wp == rp) & !gb;
124 assign full = (wp == rp) & gb;
127 always @(posedge clk)
128 if(!rst) gb <= #1 1'b0;
130 if(clr) gb <= #1 1'b0;
132 if((wp_p1 == rp) & we) gb <= #1 1'b1;
134 if(re) gb <= #1 1'b0;