1 package edu.berkeley.fleet.fpga.verilog;
2 import edu.berkeley.fleet.api.*;
3 import edu.berkeley.fleet.two.*;
4 import edu.berkeley.fleet.*;
5 import java.lang.reflect.*;
6 import edu.berkeley.sbp.chr.*;
7 import edu.berkeley.sbp.misc.*;
8 import edu.berkeley.sbp.meta.*;
9 import edu.berkeley.sbp.util.*;
12 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
14 public class Verilog {
16 public static class SimpleValue implements Value {
17 public final String s;
18 public SimpleValue(String s) { this.s = s; }
19 public SimpleValue(String s, int high, int low) { this.s = s+"["+high+":"+low+"]"; }
20 public Value getBits(int high, int low) { return new SimpleValue(s, high, low); }
21 public Assignable getAssignableBits(int high, int low) { return new SimpleValue(s, high, low); }
22 public String getVerilogName() { return s; }
23 public String toString() { return s; }
26 public static class CatValue implements Value {
27 private final Value[] values;
28 public CatValue(Value[] values) { this.values = values; }
29 public Value getBits(int high, int low) {
30 throw new RuntimeException();
32 public Assignable getAssignableBits(int high, int low) {
33 throw new RuntimeException();
35 public String toString() { return getVerilogName(); }
36 public String getVerilogName() {
37 StringBuffer sb = new StringBuffer();
40 for(int i=0; i<values.length; i++) {
41 if (values[i]==null) continue;
42 if (!first) sb.append(", ");
43 sb.append(values[i].getVerilogName());
51 public static interface Action {
52 public String getVerilogAction();
55 public static interface Trigger {
56 public String getVerilogTrigger();
57 public Trigger invert();
60 public static class InvertedTrigger implements Trigger {
61 private final Trigger original;
62 public InvertedTrigger(Trigger original) { this.original = original; }
63 public String getVerilogTrigger() { return "!("+original.getVerilogTrigger()+")"; }
64 public Trigger invert() { return original; }
67 public static interface Assignable {
68 public String getVerilogName();
69 public Assignable getAssignableBits(int high, int low);
72 public static interface Value extends Assignable {
73 public String getVerilogName();
74 public Value getBits(int high, int low);
77 public static class ConditionalAction implements Action {
78 public String condition;
80 public ConditionalAction(String condition, Action action) {
81 this.condition = condition;
84 public String toString() { return getVerilogAction(); }
85 public String getVerilogAction() { return "if ("+condition+") begin "+action.getVerilogAction()+" end"; }
88 public static class ConditionalTrigger implements Trigger {
89 public String condition;
90 public Trigger trigger;
91 public ConditionalTrigger(String condition, Trigger trigger) {
92 this.condition = condition;
93 this.trigger = trigger;
94 if (trigger instanceof Module.Port)
95 ((Module.Port)trigger).hasLatch = true;
97 public String getVerilogTrigger() {
98 return "&& (("+condition+") ? (1 " + trigger.getVerilogTrigger() + ") : 1)";
100 public Trigger invert() { return new InvertedTrigger(this); }
103 public static class SimpleAssignable implements Assignable {
104 public final String s;
105 public SimpleAssignable(String s) { this.s = s; }
106 public String getVerilogName() { return s; }
107 public Assignable getAssignableBits(int high, int low) { return new SimpleValue(s, high, low); }
110 public static class AssignAction implements Action {
113 public AssignAction(Assignable left, Value right) {
114 this.left = left.getVerilogName();
115 this.right = right.getVerilogName().toString();
117 public AssignAction(Assignable left, String right) {
118 this.left = left.getVerilogName();
121 public String getVerilogAction() { return left + "<=" + right + ";"; }
122 public String toString() { return getVerilogAction(); }
125 public static class SimpleAction implements Action {
126 public final String verilog;
127 public SimpleAction(String verilog) { this.verilog = verilog; }
128 public String getVerilogAction() { return verilog; }
129 public String toString() { return verilog; }
132 public static class Module {
133 public void dump(String prefix) throws IOException {
134 PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v")));
137 for(InstantiatedModule m : instantiatedModules)
138 m.module.dump(prefix);
141 public final String name;
142 public String getName() { return name; }
143 public Port getPort(String name) { return ports.get(name); }
145 public HashSet<InstantiatedModule> instantiatedModules = new HashSet<InstantiatedModule>();
146 public final ArrayList<Event> events = new ArrayList<Event>();
148 // FIXME: always-alphabetical convention?
149 public final HashMap<String,Port> ports = new HashMap<String,Port>();
150 public final ArrayList<String> portorder = new ArrayList<String>();
151 public final HashMap<String,StateWire> statewires = new HashMap<String,StateWire>();
152 public final HashMap<String,Latch> latches = new HashMap<String,Latch>();
154 public StringBuffer crap = new StringBuffer();
155 public StringBuffer precrap = new StringBuffer();
156 //public void addCrap(String s) { crap.append(s); crap.append('\n'); }
157 public void addPreCrap(String s) { precrap.append(s); precrap.append('\n'); }
158 public void addPreCrap0(String s) { precrap.append(s); }
160 public Module(String name) {
164 public SourcePort createInputPort(String name, int width) {
165 if (ports.get(name)!=null) throw new RuntimeException();
166 return new SourcePort(name, width, true);
168 public SourcePort getInputPort(String name) {
169 SourcePort ret = (SourcePort)ports.get(name);
170 if (ret==null) throw new RuntimeException();
173 public SinkPort createOutputPort(String name, int width, String resetBehavior) {
174 if (ports.get(name)!=null) throw new RuntimeException();
175 return new SinkPort(name, width, true, resetBehavior);
177 public SinkPort createWirePort(String name, int width) {
178 if (ports.get(name)!=null) throw new RuntimeException();
179 return new SinkPort(name, width, false, "");
181 public SourcePort createWireSourcePort(String name, int width) {
182 if (ports.get(name)!=null) throw new RuntimeException();
183 return new SourcePort(name, width, false);
185 public SinkPort getOutputPort(String name) {
186 SinkPort ret = (SinkPort)ports.get(name);
187 if (ret==null) throw new RuntimeException();
191 public class StateWire {
192 public final String name;
193 public final boolean initiallyFull;
194 public String getName() { return name; }
195 public Action isFull() { return new SimpleAction(name+"==1"); }
196 public Action isEmpty() { return new SimpleAction(name+"==0"); }
197 public Action doFill() { return new SimpleAction(name+"<=1;"); }
198 public Action doDrain() { return new SimpleAction(name+"<=0;"); }
199 public String doReset() { return name+"<="+(initiallyFull?"1":"0")+";"; }
200 public StateWire(String name) { this(name, false); }
201 public StateWire(String name, boolean initiallyFull) {
203 this.initiallyFull = initiallyFull;
204 statewires.put(name, this);
206 public void dump(PrintWriter pw) {
207 pw.println(" reg "+name+";");
208 pw.println(" initial "+name+"="+(initiallyFull?"1":"0")+";");
212 public class Latch implements Assignable, Value {
213 public final String name;
214 public final int width;
215 public final long initial;
216 public Latch(String name, int width) { this(name, width, 0); }
217 public Latch(String name, int width, long initial) {
220 this.initial = initial;
221 latches.put(name, this);
223 public String getVerilogName() { return name; }
224 public Value getBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
225 public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
226 public String doReset() { return name+"<="+initial+";"; }
227 public void dump(PrintWriter pw) {
228 pw.println(" reg ["+(width-1)+":0] "+name+";");
229 pw.println(" initial "+name+"="+initial+";");
231 public void connect(SinkPort driven) {
232 driven.latchDriver = this;
236 public abstract class Port implements Action, Assignable, Trigger {
237 public abstract String doReset();
238 public final String name;
239 public String getName() { return name; }
240 public final int width;
241 public int getWidth() { return width; }
242 public boolean hasLatch = false;
243 public boolean external;
244 public Port(String name, int width, boolean external) {
247 this.external = external;
248 ports.put(name, this);
252 public String getVerilogName() { return name; }
253 String getAck() { return name+"_a"; }
254 String getReq() { return name+"_r"; }
255 public String isFull() { return "("+name+"_r"+" && !"+name+"_a)"; }
256 public abstract String getInterface();
257 public abstract String getSimpleInterface();
258 public abstract String getDeclaration();
259 public abstract String getAssignments();
260 public abstract void connect(SinkPort driven);
261 public Trigger invert() { return new InvertedTrigger(this); }
264 public static class InstantiatedModule {
265 public final Module module;
266 public final Module thisModule;
268 public final HashMap<String,Port> ports = new HashMap<String,Port>();
269 public String getName() { return module.getName()+"_"+id; }
270 public InstantiatedModule(Module thisModule, Module module) {
271 this.thisModule = thisModule;
272 this.module = module;
273 this.id = thisModule.id++;
274 thisModule.instantiatedModules.add(this);
276 public void dump(PrintWriter pw) {
277 pw.println(" " + module.getName() + " " + getName() + "(clk, rst ");
278 for(String s : module.portorder)
279 pw.println(", " + getPort(s).getSimpleInterface());
280 if (module.name.equals("dram")) {
281 pw.println(" , dram_addr");
282 pw.println(" , dram_addr_r");
283 pw.println(" , dram_addr_a");
284 pw.println(" , dram_isread");
285 pw.println(" , dram_write_data");
286 pw.println(" , dram_write_data_push");
287 pw.println(" , dram_write_data_full");
288 pw.println(" , dram_read_data");
289 pw.println(" , dram_read_data_pop");
290 pw.println(" , dram_read_data_empty");
291 pw.println(" , dram_read_data_latency");
293 if (module.name.equals("ddr2")) {
294 pw.println(" , ddr2_addr");
295 pw.println(" , ddr2_addr_r");
296 pw.println(" , ddr2_addr_a");
297 pw.println(" , ddr2_isread");
298 pw.println(" , ddr2_write_data");
299 pw.println(" , ddr2_write_data_push");
300 pw.println(" , ddr2_write_data_full");
301 pw.println(" , ddr2_read_data");
302 pw.println(" , ddr2_read_data_pop");
303 pw.println(" , ddr2_read_data_empty");
304 pw.println(" , ddr2_read_data_latency");
306 if (module.name.equals("video")) {
307 pw.println(" , vga_clk");
308 pw.println(" , vga_psave");
309 pw.println(" , vga_hsync");
310 pw.println(" , vga_vsync");
311 pw.println(" , vga_sync");
312 pw.println(" , vga_blank");
313 pw.println(" , vga_r");
314 pw.println(" , vga_g");
315 pw.println(" , vga_b");
316 pw.println(" , vga_clkout");
320 public Port getPort(String name) {
321 return (module.ports.get(name) instanceof SinkPort) ? getOutputPort(name) : getInputPort(name);
323 public SinkPort getInputPort(String name) {
324 int width = module.getPort(name).getWidth();
325 SinkPort port = (SinkPort)ports.get(name);
327 port = thisModule.new SinkPort(getName()+"_"+name, width, false, "");
328 ports.put(name, port);
332 public SourcePort getOutputPort(String name) {
333 int width = module.getPort(name).getWidth();
334 SourcePort port = (SourcePort)ports.get(name);
336 port = thisModule.new SourcePort(getName()+"_"+name, width, false);
337 ports.put(name, port);
343 public class SourcePort extends Port implements Value {
344 public SourcePort(String name, int width, boolean external) {
345 super(name, width, external); }
346 public Value getBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
347 public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
348 public String getVerilogTrigger() { return " && " + getReq() + " && !"+getAck(); }
349 public String getVerilogAction() { return getAck() + " <= 1;"; }
350 public String getInterface() { return getReq()+", "+getAck()+"_, "+name+""; }
351 public String getSimpleInterface() { return getReq()+", "+getAck()+", "+name+""; }
352 public String testBit(int index, boolean value) {
353 return "("+name+"["+index+"]=="+(value?1:0)+")";
355 public String getDeclaration() {
356 StringBuffer sb = new StringBuffer();
358 sb.append("input " + name +"_r;\n");
359 sb.append("output " + name +"_a_;\n");
361 sb.append("input ["+(width-1)+":0]" + name +";\n");
363 sb.append("input [0:0]" + name +";\n"); // waste a bit, I guess
365 sb.append("wire " + name +"_r;\n");
367 sb.append("wire ["+(width-1)+":0]" + name +";\n");
370 sb.append("wire " + name +"_a;\n");
372 sb.append("reg " + name +"_a;\n");
373 sb.append("initial " + name +"_a = 0;\n");
375 return sb.toString();
377 public String doReset() { return hasLatch ? name+"_a<=1;" : ""; }
378 public String getAssignments() {
379 StringBuffer sb = new StringBuffer();
381 sb.append("assign " + name +"_a_ = " + name + "_a;\n");
382 return sb.toString();
384 public void connect(SinkPort driven) {
385 driven.driver = this;
388 public class SinkPort extends Port {
389 public SourcePort driver = null;
390 public boolean forceNoLatch = false;
391 public SinkPort driven = null;
392 public Value latchDriver = null;
393 public boolean noDriveLatches = false;
394 public final String resetBehavior;
395 public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
396 public String getVerilogAction() { return getReq() + " <= 1;"; }
397 public String getVerilogTrigger() { return " && !" + getReq() + " && !"+getAck(); }
398 public SinkPort(String name, int width, boolean external, String resetBehavior) {
399 super(name, width, external); this.resetBehavior=resetBehavior; }
400 public String getResetBehavior() { return resetBehavior; }
401 public String getInterface() { return name+"_r_, "+name+"_a, "+name+"_"; }
402 public String getSimpleInterface() { return name+"_r, "+name+"_a, "+name; }
403 public String getDeclaration() {
404 StringBuffer sb = new StringBuffer();
406 sb.append("output " + name +"_r_;\n");
407 sb.append("input " + name +"_a;\n");
409 sb.append("output ["+(width-1)+":0]" + name +"_;\n");
411 sb.append("output [0:0]" + name +"_;\n"); // waste a bit, I guess
413 sb.append("wire " + name +"_a;\n");
416 if (forceNoLatch || latchDriver!=null) {
417 sb.append("reg " + name +"_r;\n");
418 sb.append("initial " + name +"_r = 0;\n");
420 sb.append("wire ["+(width-1)+":0]" + name +";\n");
421 } else if (!hasLatch) {
422 sb.append("wire " + name +"_r;\n");
424 sb.append("wire ["+(width-1)+":0]" + name +";\n");
426 sb.append("reg " + name +"_r;\n");
427 sb.append("initial " + name +"_r = 0;\n");
429 sb.append("reg ["+(width-1)+":0]" + name +";\n");
430 if (!"/*NORESET*/".equals(resetBehavior))
431 sb.append("initial " + name +" = 0;\n");
434 return sb.toString();
436 public String doReset() {
437 return (forceNoLatch||latchDriver!=null||width==0)
440 ? (name+"_r<=0; "+("/*NORESET*/".equals(resetBehavior) ? "" : (name+"<=0;")))
443 public String getAssignments() {
444 StringBuffer sb = new StringBuffer();
446 sb.append("assign " + name +"_r_ = " + name + "_r;\n");
448 sb.append("assign " + name +"_ = " + name + ";\n");
450 if (driven != null) {
451 sb.append("assign " + driven.name +"_r = " + name + "_r;\n");
452 sb.append("assign " + name +"_a = " + driven.name + "_a;\n");
454 sb.append("assign " + driven.name +" = " + name + ";\n");
456 if (driver != null) {
457 sb.append("assign " + name +"_r = " + driver.name + "_r;\n");
458 sb.append("assign " + driver.name +"_a = " + name + "_a;\n");
459 if (width>0 && !noDriveLatches)
460 sb.append("assign " + name +" = " + driver.name + ";\n");
462 if (latchDriver != null) {
464 sb.append("assign " + name +" = " + latchDriver.getVerilogName() + ";\n");
466 return sb.toString();
468 public void connect(SinkPort driven) {
469 this.driven = driven;
470 throw new RuntimeException();
474 public void dump(PrintWriter pw, boolean fix) {
475 pw.println("module "+name+"(clk, rst ");
476 for(String name : portorder) {
477 Port p = ports.get(name);
478 pw.println(" , " + p.getInterface());
480 if (this.name.equals("root")) {
481 pw.println(" , dram_addr");
482 pw.println(" , dram_addr_r");
483 pw.println(" , dram_addr_a");
484 pw.println(" , dram_isread");
485 pw.println(" , dram_write_data");
486 pw.println(" , dram_write_data_push");
487 pw.println(" , dram_write_data_full");
488 pw.println(" , dram_read_data");
489 pw.println(" , dram_read_data_pop");
490 pw.println(" , dram_read_data_empty");
491 pw.println(" , dram_read_data_latency");
492 pw.println(" , vga_clk");
493 pw.println(" , vga_psave");
494 pw.println(" , vga_hsync");
495 pw.println(" , vga_vsync");
496 pw.println(" , vga_sync");
497 pw.println(" , vga_blank");
498 pw.println(" , vga_r");
499 pw.println(" , vga_g");
500 pw.println(" , vga_b");
501 pw.println(" , vga_clkout");
502 pw.println(" , ddr2_addr");
503 pw.println(" , ddr2_addr_r");
504 pw.println(" , ddr2_addr_a");
505 pw.println(" , ddr2_isread");
506 pw.println(" , ddr2_write_data");
507 pw.println(" , ddr2_write_data_push");
508 pw.println(" , ddr2_write_data_full");
509 pw.println(" , ddr2_read_data");
510 pw.println(" , ddr2_read_data_pop");
511 pw.println(" , ddr2_read_data_empty");
512 pw.println(" , ddr2_read_data_latency");
516 pw.println(" input clk;");
517 pw.println(" input rst;");
518 if (this.name.equals("root")) {
519 pw.println("output [31:0] dram_addr;");
520 pw.println("output dram_addr_r;");
521 pw.println("input dram_addr_a;");
522 pw.println("output dram_isread;");
523 pw.println("output [63:0] dram_write_data;");
524 pw.println("output dram_write_data_push;");
525 pw.println("input dram_write_data_full;");
526 pw.println("input [63:0] dram_read_data;");
527 pw.println("output dram_read_data_pop;");
528 pw.println("input dram_read_data_empty;");
529 pw.println("input [1:0] dram_read_data_latency;");
530 pw.println("output [31:0] ddr2_addr;");
531 pw.println("output ddr2_addr_r;");
532 pw.println("input ddr2_addr_a;");
533 pw.println("output ddr2_isread;");
534 pw.println("output [63:0] ddr2_write_data;");
535 pw.println("output ddr2_write_data_push;");
536 pw.println("input ddr2_write_data_full;");
537 pw.println("input [63:0] ddr2_read_data;");
538 pw.println("output ddr2_read_data_pop;");
539 pw.println("input ddr2_read_data_empty;");
540 pw.println("input [1:0] ddr2_read_data_latency;");
541 pw.println("input vga_clk;");
542 pw.println("output vga_psave;");
543 pw.println("output vga_hsync;");
544 pw.println("output vga_vsync;");
545 pw.println("output vga_sync;");
546 pw.println("output vga_blank;");
547 pw.println("output [7:0] vga_r;");
548 pw.println("output [7:0] vga_g;");
549 pw.println("output [7:0] vga_b;");
550 pw.println("output vga_clkout;");
552 for(String name : ports.keySet()) {
553 Port p = ports.get(name);
554 pw.println(" " + p.getDeclaration());
556 for(StateWire sw : statewires.values())
558 for(Latch l : latches.values())
560 for(String name : ports.keySet()) {
561 Port p = ports.get(name);
562 pw.println(" " + p.getAssignments());
564 for(InstantiatedModule m : instantiatedModules) {
568 pw.println("always @(posedge clk) begin");
569 pw.println(" if (!rst) begin");
570 for(Latch l : latches.values())
571 pw.println(l.doReset());
572 for(StateWire sw : statewires.values())
573 pw.println(sw.doReset());
574 for(Port p : ports.values())
575 pw.println(p.doReset());
576 pw.println(" end else begin");
577 for(Port p : ports.values()) {
578 if (p instanceof SourcePort) {
579 SourcePort ip = (SourcePort)p;
581 pw.println("if (!"+ip.getReq()+" && "+ip.getAck()+") "+ip.getAck()+"<=0;");
583 SinkPort op = (SinkPort)p;
585 pw.println("if ("+op.getReq()+" && "+op.getAck()+") begin "+
587 op.getResetBehavior()+" end");
590 for(Event a : events) a.dump(pw, fix);
591 pw.println(" begin end");
596 pw.println("endmodule");
600 public Object[] triggers;
601 public Object[] actions;
602 public Event(Object[] triggers, Object action) { this(triggers, new Object[] { action }); }
603 public Event(Object[] triggers, Object[] actions) {
604 Module.this.events.add(this);
605 this.triggers = triggers;
606 this.actions = actions;
607 for(int i=0; i<triggers.length; i++)
608 if (triggers[i] instanceof Port)
609 ((Port)triggers[i]).hasLatch = true;
611 public void dump(PrintWriter pw, boolean fix) {
613 for(Object o : triggers) {
614 if (o instanceof Trigger) pw.print(((Trigger)o).getVerilogTrigger());
615 else pw.print(" && " + o);
617 pw.println(") begin ");
618 for(Object a : actions) if (a!=null) pw.println(((Action)a).getVerilogAction());
619 if (fix) pw.println("end /*else*/ ");
620 else pw.println("end else ");