7 out_r_, out_a, out_d_);
10 `input(a_r, a_a, a_a_, [(`DATAWIDTH-1):0], a_d)
11 `input(b_r, b_a, b_a_, [(`DATAWIDTH-1):0], b_d)
12 `input(op_r, op_a, op_a_, [(`DATAWIDTH-1):0], op_d)
13 `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
14 `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
17 reg [(`DATAWIDTH-1):0] reg_a;
19 reg [(`DATAWIDTH-1):0] reg_b;
21 reg [(`DATAWIDTH-1):0] reg_op;
23 always @(posedge clk) begin
25 `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
28 `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
31 `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
34 if (have_a && have_b && have_op) begin
36 0: out_d = reg_a + reg_b;
37 1: out_d = reg_a - reg_b;
38 //2: out_d = reg_a * reg_b; // will not synthesize --AM
39 //3: out_d = reg_a / reg_b; // will not synthesize --AM
40 //4: out_d = reg_a % reg_b; // will not synthesize --AM
43 `onwrite(out_r, out_a)