src/edu/berkeley/fleet/slipway/bram.inc

   1 module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
   2     input  clk;
   3     input  we;
   4     input  [(`BRAM_ADDR_WIDTH-1):0] a;
   5     input  [(`BRAM_ADDR_WIDTH-1):0] dpra;
   6     input  [(`BRAM_DATA_WIDTH-1):0] di;
   7     output [(`BRAM_DATA_WIDTH-1):0] spo;
   8     output [(`BRAM_DATA_WIDTH-1):0] dpo;
   9     reg    [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
  10     reg    [(`BRAM_ADDR_WIDTH-1):0] read_a;
  11     reg    [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
  12     always @(posedge clk) begin
  13         if (we)
  14             ram[a] <= di;
  15         read_a <= a;
  16         read_dpra <= dpra;
  17     end
  18     assign spo = ram[read_a];
  19     assign dpo = ram[read_dpra];
  20 endmodule