major fpga code reorg; added icache+dcache
[fleet.git] / src / edu / berkeley / fleet / slipway / execute.inc
1   `input(command_r,   command_a,   command_a_, [(`DATAWIDTH-1):0], command_d)
2   `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
3   `defreg(ihorn_d_,                   [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
4   `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
5   `defreg(dhorn_d_,                   [(`PACKET_WIDTH-1):0], dhorn_d)
6
7   reg ihorn_full;
8   reg dhorn_full;
9
10   always @(posedge clk) begin
11     if (ihorn_full) begin
12       `onwrite(ihorn_r, ihorn_a)
13         ihorn_full = 0;
14       end
15     end else if (dhorn_full) begin
16       `onwrite(dhorn_r, dhorn_a)
17         dhorn_full = 0;
18       end
19     end else begin
20       `onread(command_r, command_a)
21         case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
22           0: begin
23               ihorn_full  = 1;
24               ihorn_d = command_d;
25               end
26           //01:
27           2: begin
28               dhorn_full  = 1;
29               `packet_data(dhorn_d) = command_d[23:0];
30               `packet_dest(dhorn_d) = command_d[34:24];
31               end
32           //11:
33         endcase
34       end
35     end
36   end