src/edu/berkeley/fleet/slipway/horn.inc

   1 (clk,
   2             in_r,  in_a_, in_d,
   3             out0_r_, out0_a,  out0_d_,
   4             out1_r_, out1_a,  out1_d_);
   5
   6   input                  clk;
   7   reg                    full;
   8   reg                    dir;
   9   initial                full=0;
  10
  11   `input(in_r,    in_a,    in_a_,   [`XWIDTH:0], in_d)
  12   `output(out0_r, out0_r_, out0_a,  [`XWIDTH:0], out0_d_)
  13   `output(out1_r, out1_r_, out1_a,  [`XWIDTH:0], out1_d_)
  14   `defreg(dat_, [`XWIDTH:0], dat)
  15
  16   assign out0_d_ = dat_;
  17   assign out1_d_ = dat_;
  18
  19   always @(posedge clk) begin
  20     if (full) begin
  21       if (dir==0) begin
  22         `onwrite(out0_r, out0_a)
  23           full = 0;
  24         end
  25       end else begin
  26         `onwrite(out1_r, out1_a)
  27           full = 0;
  28         end
  29       end
  30     end else begin
  31       `onread(in_r, in_a)
  32         full  = 1;
  33         dat   = in_d;
  34         dir   = `dest_steer(dat);
  35         `dest(dat) = `dest(dat) >> 1;
  36       end
  37     end
  38   end
  39
  40 endmodule