2 `define BRAM_ADDR_WIDTH 14
3 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
4 `define BRAM_NAME icache_bram
8 write_addr_r, write_addr_a_, write_addr_d,
9 write_data_r, write_data_a_, write_data_d,
10 write_done_r_, write_done_a, write_done_d_,
12 preload_r, preload_a_, preload_d,
13 ihorn_r_, ihorn_a, ihorn_d_,
14 dhorn_r_, dhorn_a, dhorn_d_
18 `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
19 `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
20 `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
21 `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
23 `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
24 `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
25 `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
26 `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
27 `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
28 `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
31 initial ihorn_full = 0;
33 initial dhorn_full = 0;
35 initial command_valid = 0;
37 reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
38 reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
39 initial preload_size = 0;
41 reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
42 reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
43 reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
44 reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
45 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
46 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
47 reg [(`INSTRUCTION_WIDTH-1):0] command;
48 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
51 reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
52 reg [(`DATAWIDTH-1):0] data;
55 reg [(`BRAM_ADDR_WIDTH-1):0] write_addr;
56 reg [(`BRAM_DATA_WIDTH-1):0] write_data;
58 wire [(`BRAM_DATA_WIDTH-1):0] ramread;
60 reg command_valid_read;
61 initial command_valid_read = 0;
66 icache_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
68 always @(posedge clk) begin
72 if (!write_addr_r && write_addr_a) write_addr_a = 0;
73 if (!write_data_r && write_data_a) write_data_a = 0;
75 if (command_valid_read) begin
76 command_valid_read <= 0;
79 end else if (send_done) begin
80 `onwrite(write_done_r, write_done_a)
84 end else if (write_addr_r && write_data_r) begin
89 write_addr <= write_addr_d;
90 write_data <= write_data_d;
92 end else if (ihorn_full && launched) begin
93 `onwrite(ihorn_r, ihorn_a)
97 end else if (dhorn_full) begin
98 `onwrite(dhorn_r, dhorn_a)
102 end else if (command_valid) begin
105 case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
112 temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
113 temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
114 data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
115 data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
116 `packet_data(dhorn_d) <= temp;
117 `packet_dest(dhorn_d) <=
118 command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
122 `packet_data(dhorn_d) <= command[23:0];
123 `packet_dest(dhorn_d) <= command[34:24];
127 `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from;
128 `packet_dest(dhorn_d) <= command[34:24];
132 end else if (cbd_pos < cbd_size) begin
133 current_instruction_read_from <= cbd_base+cbd_pos;
134 command_valid_read <= 1;
135 cbd_pos <= cbd_pos + 1;
138 `onread(cbd_r, cbd_a)
140 cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
141 cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
144 `onread(preload_r, preload_a)
145 if (preload_size == 0) begin
146 preload_size <= preload_d;
147 end else if (!launched) begin
149 write_data <= preload_d;
150 write_addr <= preload_pos;
151 if (preload_pos == 0) begin
152 temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
153 temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
155 if ((preload_pos+1) == preload_size) begin
157 cbd_base <= temp_base;
158 cbd_size <= temp_size;
161 preload_pos <= preload_pos + 1;