src/edu/berkeley/fleet/slipway/icache.v

   1 `include "macros.v"
   2 `define BRAM_ADDR_WIDTH 14
   3 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
   4 `define BRAM_NAME icache_bram
   5 `include "bram.inc"
   6
   7 module icache (clk,
   8                write_addr_r,   write_addr_a_,  write_addr_d,
   9                write_data_r,   write_data_a_,  write_data_d,
  10                write_done_r_,  write_done_a,   write_done_d_,
  11                cbd_r,          cbd_a_,         cbd_d,
  12                preload_r,      preload_a_,     preload_d,
  13                ihorn_r_,       ihorn_a,        ihorn_d_,
  14                dhorn_r_,       dhorn_a,        dhorn_d_
  15            );
  16
  17   input  clk;
  18   `input(write_addr_r,   write_addr_a,  write_addr_a_,  [(`DATAWIDTH-1):0],         write_addr_d)
  19   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
  20   `output(write_done_r,  write_done_r_, write_done_a,   [(`DATAWIDTH-1):0],         write_done_d_)
  21   `defreg(write_done_d_,                                [(`DATAWIDTH-1):0],         write_done_d)
  22
  23   `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
  24   `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
  25   `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
  26   `defreg(ihorn_d_,                                     [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
  27   `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
  28   `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
  29
  30   reg ihorn_full;
  31   reg dhorn_full;
  32   reg command_valid;
  33
  34   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
  35   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
  36   initial preload_size = 0;
  37
  38   reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
  39   reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
  40   reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
  41   reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
  42   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
  43   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
  44   reg [(`INSTRUCTION_WIDTH-1):0]  command;
  45   reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
  46   reg                             send_done;
  47
  48   reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
  49   reg [(`DATAWIDTH-1):0]                                     data;
  50
  51   reg                             write_flag;
  52   reg [(`BRAM_ADDR_WIDTH-1):0]    write_addr;
  53   reg [(`BRAM_DATA_WIDTH-1):0]    write_data;
  54
  55   wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
  56
  57   reg command_valid_read;
  58
  59   reg launched;
  60   initial launched = 0;
  61
  62   icache_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
  63
  64   always @(posedge clk) begin
  65
  66     write_flag <= 0;
  67
  68     if (!write_addr_r && write_addr_a) write_addr_a = 0;
  69     if (!write_data_r && write_data_a) write_data_a = 0;
  70
  71     if (command_valid_read) begin
  72       command_valid_read  <= 0;
  73       command_valid       <= 1;
  74
  75     end else  if (send_done) begin
  76       `onwrite(write_done_r, write_done_a)
  77         send_done <= 0;
  78       end
  79
  80     end else if (write_addr_r && write_data_r) begin
  81       write_addr_a       = 1;
  82       write_data_a       = 1;
  83       send_done         <= 1;
  84       write_flag        <= 1;
  85       write_addr        <= write_addr_d;
  86       write_data        <= write_data_d;
  87
  88     end else if (ihorn_full) begin
  89       `onwrite(ihorn_r, ihorn_a)
  90         ihorn_full <= 0;
  91       end
  92
  93     end else if (dhorn_full) begin
  94       `onwrite(dhorn_r, dhorn_a)
  95         dhorn_full <= 0;
  96       end
  97
  98     end else if (command_valid) begin
  99       command_valid <= 0;
 100       command = ramread;
 101       case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
 102         0: begin
 103             ihorn_full  <= 1;
 104             ihorn_d     <= command;
 105            end
 106         1: begin
 107             dhorn_full  <= 1;
 108             temp    = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
 109             temp    = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
 110             data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
 111             data[(`CODEBAG_SIZE_BITS-1):0]            = command[(`CODEBAG_SIZE_BITS-1):0];
 112             `packet_data(dhorn_d) <= temp;
 113             `packet_dest(dhorn_d) <=
 114                   command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
 115            end
 116         2: begin
 117             dhorn_full            <= 1;
 118             `packet_data(dhorn_d) <= command[23:0];
 119             `packet_dest(dhorn_d) <= command[34:24];
 120            end
 121         3: begin
 122             dhorn_full            <= 1;
 123             `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from;
 124             `packet_dest(dhorn_d) <= command[34:24];
 125            end
 126       endcase
 127
 128     end else if (cbd_pos < cbd_size) begin
 129       current_instruction_read_from <= cbd_base+cbd_pos;
 130       command_valid_read            <= 1;
 131       cbd_pos                       <= cbd_pos + 1;
 132
 133     end else begin
 134       `onread(cbd_r, cbd_a)
 135         cbd_pos       <= 0;
 136         cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
 137         cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
 138
 139       end else begin
 140         `onread(preload_r, preload_a)
 141           if (preload_size == 0) begin
 142             preload_size     <= preload_d;
 143           end else if (!launched) begin
 144             write_flag <= 1;
 145             write_data <= preload_d;
 146             write_addr <= preload_pos;
 147             if (preload_pos == 0) begin
 148               temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
 149               temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
 150             end
 151             if ((preload_pos+1) == preload_size) begin
 152               cbd_pos  <= 0;
 153               cbd_base <= temp_base;
 154               cbd_size <= temp_size;
 155               launched <= 1;
 156             end
 157             preload_pos      <= preload_pos + 1;
 158           end
 159         end
 160       end
 161     end
 162 /*
 163     if (write_flag) begin
 164       write_flag = 0;
 165       ram[write_addr]  <= write_data;
 166     end
 167 */
 168   end
 169 endmodule
 170
 171