src/edu/berkeley/fleet/slipway/icache.v

   1 `include "macros.v"
   2 `define BRAM_ADDR_WIDTH 8
   3 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
   4 `define BRAM_NAME icache_bram
   5 `include "bram.inc"
   6
   7 module icache (clk,
   8                write_addr_r,   write_addr_a_,  write_addr_d,
   9                write_data_r,   write_data_a_,  write_data_d,
  10                write_done_r_,  write_done_a,   write_done_d_,
  11                cbd_r,          cbd_a_,         cbd_d,
  12                preload_r,      preload_a_,     preload_d,
  13                ihorn_r_,       ihorn_a,        ihorn_d_,
  14                dhorn_r_,       dhorn_a,        dhorn_d_
  15            );
  16
  17   input  clk;
  18   `input(write_addr_r,   write_addr_a,  write_addr_a_,  [(`DATAWIDTH-1):0],         write_addr_d)
  19   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
  20   `output(write_done_r,  write_done_r_, write_done_a,   [(`DATAWIDTH-1):0],         write_done_d_)
  21   `defreg(write_done_d_,                                [(`DATAWIDTH-1):0],         write_done_d)
  22
  23   `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
  24   `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
  25   `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
  26   `defreg(ihorn_d_,                                     [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
  27   `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
  28   `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
  29
  30   reg ihorn_full;
  31   reg dhorn_full;
  32   reg command_valid;
  33
  34   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
  35   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
  36   reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
  37   reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
  38   reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
  39   reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
  40   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
  41   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
  42   reg [(`INSTRUCTION_WIDTH-1):0]  command;
  43   reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
  44   reg                             send_done;
  45
  46   reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
  47   reg [(`DATAWIDTH-1):0]                                     data;
  48
  49   reg                             write_flag;
  50   reg [(`BRAM_ADDR_WIDTH-1):0]    write_addr;
  51   reg [(`BRAM_DATA_WIDTH-1):0]    write_data;
  52
  53   wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
  54
  55   reg command_valid_read;
  56
  57   always @(posedge clk) begin
  58
  59     if (command_valid_read) begin
  60       command_valid  <= 1;
  61       command        <= ramread;
  62     end
  63
  64     if (!write_addr_r && write_addr_a) write_addr_a = 0;
  65     if (!write_data_r && write_data_a) write_data_a = 0;
  66
  67     if (send_done) begin
  68       `onwrite(write_done_r, write_done_a)
  69         send_done <= 0;
  70       end
  71
  72     end else if (write_addr_r && write_data_r) begin
  73       write_addr_a       = 1;
  74       write_data_a       = 1;
  75       send_done         <= 1;
  76       write_flag         = 1;
  77       write_addr         = write_addr_d;
  78       write_data         = write_data_d;
  79
  80     end else if (ihorn_full) begin
  81       `onwrite(ihorn_r, ihorn_a)
  82         ihorn_full <= 0;
  83       end
  84
  85     end else if (dhorn_full) begin
  86       `onwrite(dhorn_r, dhorn_a)
  87         dhorn_full <= 0;
  88       end
  89
  90     end else if (command_valid) begin
  91       command_valid <= 0;
  92       case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
  93         0: begin
  94             ihorn_full  <= 1;
  95             ihorn_d     <= command;
  96            end
  97         1: begin
  98             dhorn_full  <= 1;
  99             temp    = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
 100             temp    = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
 101             data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
 102             data[(`CODEBAG_SIZE_BITS-1):0]            = command[(`CODEBAG_SIZE_BITS-1):0];
 103             `packet_data(dhorn_d) <= temp;
 104             `packet_dest(dhorn_d) <=
 105                   command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
 106            end
 107         2: begin
 108             dhorn_full            <= 1;
 109             `packet_data(dhorn_d) <= command[23:0];
 110             `packet_dest(dhorn_d) <= command[34:24];
 111            end
 112         3: begin
 113             dhorn_full            <= 1;
 114             `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from;
 115             `packet_dest(dhorn_d) <= command[34:24];
 116            end
 117       endcase
 118
 119     end else if (cbd_pos < cbd_size) begin
 120       command_valid                 <= 1;
 121       current_instruction_read_from =  cbd_base+cbd_pos;
 122       command                       <= ram[current_instruction_read_from];
 123       cbd_pos                       <= cbd_pos + 1;
 124
 125     end else begin
 126       `onread(cbd_r, cbd_a)
 127         cbd_pos       <= 0;
 128         cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
 129         cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
 130
 131       end else begin
 132         `onread(preload_r, preload_a)
 133           if (preload_size == 0) begin
 134             preload_size     <= preload_d;
 135           end else begin
 136             write_flag = 1;
 137             write_data = preload_d;
 138             write_addr = preload_pos;
 139             if (preload_pos == 0) begin
 140               temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
 141               temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
 142             end
 143             if ((preload_pos+1) == preload_size) begin
 144               cbd_pos  <= 0;
 145               cbd_base <= temp_base;
 146               cbd_size <= temp_size;
 147             end
 148             preload_pos      <= preload_pos + 1;
 149           end
 150         end
 151       end
 152     end
 153
 154     if (write_flag) begin
 155       write_flag = 0;
 156       ram[write_addr]  <= write_data;
 157     end
 158   end
 159 endmodule
 160
 161