2 `define CODEBAG_SIZE_BITS 6
3 `define BENKOBOX_ADDRESS_BITS 11
4 `define DESTINATION_ADDRESS_BITS 11
7 `define PACKET_WIDTH (`DATAWIDTH + `DESTINATION_ADDRESS_BITS)
8 `define INSTRUCTION_WIDTH 37
10 `define packet_data(p) p[(`DESTINATION_ADDRESS_BITS+`DATAWIDTH-1):(`DESTINATION_ADDRESS_BITS)]
11 `define INSTRUCTION_BENKOBOX_OFFSET (1+`COUNT_BITS+`DESTINATION_ADDRESS_BITS+5)
12 `define packet_dest(p) p[(`DESTINATION_ADDRESS_BITS-1):0]
13 `define instruction_dest(i) i[(24+11-1):24]
14 `define packet_dest_steer(p) p[0]
15 `define instruction_dest_steer(i) i[24]
17 `define opcode_base (1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS)
18 `define instruction_bit_tokenout(instruction) instruction[`opcode_base+4]
19 `define instruction_bit_dataout(instruction) instruction[`opcode_base+3]
20 `define instruction_bit_latch(instruction) instruction[`opcode_base+2]
21 `define instruction_bit_datain(instruction) instruction[`opcode_base+1]
22 `define instruction_bit_tokenin(instruction) instruction[`opcode_base+0]
23 `define instruction_bit_dest(instruction) instruction[(`DESTINATION_ADDRESS_BITS):1]
24 `define instruction_bit_recycle(instruction) instruction[0]
25 `define instruction_is_kill(i) (`instruction_bit_latch(i) && (!(`instruction_bit_datain(i))))
26 `define instruction_bit_kill_only_standing(i) (`instruction_bit_tokenin(i))
27 `define instruction_count(instruction) instruction[(1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS-1):(1+`DESTINATION_ADDRESS_BITS)]
29 `define instruction_is_clog(instruction) (`instruction_count(instruction)==0 && !`instruction_bit_tokenin(instruction) && !`instruction_bit_datain(instruction) && !`instruction_bit_tokenout(instruction) && !`instruction_bit_dataout(instruction))
30 `define instruction_is_unclog(instruction) (`instruction_bit_kill_only_standing(instruction) && `instruction_is_kill(instruction))
32 `define defreg(signame,width,regname) reg width regname; wire width signame; assign signame = regname; initial regname = 0;
33 `define input(r, a, a_, w, d) input r; output a_; reg a; assign a_=a; input w d; initial a=0;
34 `define output(r, r_, a, w, d) output r_; input a; reg r; assign r_=r; output w d; initial r=0;
36 `define onread(req, ack) if (!req && ack) ack <= 0; else if (req && !ack) begin ack <=1;
37 `define onwrite(req, ack) if (!req && !ack) req <= 1; else if (req && ack) begin req <= 0;