src/edu/berkeley/fleet/slipway/macros.v

   1 `define DATAWIDTH                37
   2 `define CODEBAG_SIZE_BITS        6
   3 `define BENKOBOX_ADDRESS_BITS    11
   4 `define DESTINATION_ADDRESS_BITS 11
   5 `define COUNT_BITS               7
   6 `define PACKET_WIDTH             (`DATAWIDTH + `DESTINATION_ADDRESS_BITS)
   7 `define INSTRUCTION_WIDTH        37
   8
   9 `define packet_data(p)              p[(`DESTINATION_ADDRESS_BITS+`DATAWIDTH-1):(`DESTINATION_ADDRESS_BITS)]
  10 `define INSTRUCTION_BENKOBOX_OFFSET (1+`COUNT_BITS+`DESTINATION_ADDRESS_BITS+5)
  11 `define packet_dest(p)              p[(`DESTINATION_ADDRESS_BITS-1):0]
  12 `define instruction_dest(i)         i[(24+11-1):24]
  13 `define packet_dest_steer(p)        p[0]
  14 `define instruction_dest_steer(i)   i[24]
  15
  16 `define opcode_base (1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS)
  17 `define instruction_bit_tokenin(instruction)  instruction[`opcode_base+4]
  18 `define instruction_bit_datain(instruction)   instruction[`opcode_base+3]
  19 `define instruction_bit_latch(instruction)    instruction[`opcode_base+2]
  20 `define instruction_bit_dataout(instruction)  instruction[`opcode_base+1]
  21 `define instruction_bit_tokenout(instruction) instruction[`opcode_base+0]
  22 `define instruction_bit_dest(instruction)     instruction[(`DESTINATION_ADDRESS_BITS):1]
  23
  24 `define defreg(signame,width,regname) reg width regname; wire width signame;  assign signame = regname; initial regname = 0;
  25 `define onread(req, ack)              if (!req && ack) ack=0;        else if (req && !ack) begin ack=1;
  26 `define onwrite(out_r, out_a)         if (out_r && out_a) out_r = 0; else if (!out_r && !out_a) begin out_r = 1;
  27 `define input(r, a, a_, w, d)  input r;  output a_; reg a; assign a_=a; input  w d;
  28 `define output(r, r_, a, w, d) output r_; input a;  reg r; assign r_=r; output w d;