src/edu/berkeley/fleet/slipway/root.v

   1 `include "macros.v"
   2
   3 module root(clk, in_r,   in_a_, in_d,
   4                  out_r_, out_a, out_d_);
   5
   6   input        clk;
   7
   8   `input(in_r,   in_a, in_a_,  [7:0], in_d)
   9   `output(out_r, out_r_, out_a,  [7:0], out_d_)
  10
  11   `defreg(horn_in_r_, [0:0],          horn_in_r)
  12   `defreg(horn_in_d_, [(`PACKET_WIDTH-1):0], horn_in_d)
  13   `defreg(funnel_out_a_, [0:0],       funnel_out_a)
  14
  15   reg [(`DATAWIDTH-1):0] out_d;
  16   assign out_d_ = out_d[7:0];
  17
  18   reg [7:0]          count_in;
  19   reg [7:0]          count_out;
  20   reg                full_in;
  21   reg                full_out;
  22
  23   initial full_in   = 0;
  24   initial count_in  = 0;
  25   initial full_out  = 0;
  26   initial count_out = 0;
  27
  28   wire [(`DATAWIDTH-1):0] funnel_out_d;
  29   fabric fabric(clk, horn_in_r,   horn_in_a,   horn_in_d_,
  30                      funnel_out_r, funnel_out_a, funnel_out_d);
  31
  32   always @(posedge clk) begin
  33     if (!full_in) begin
  34       `onread(in_r, in_a)
  35           horn_in_d = (horn_in_d << 8) | in_d;
  36           count_in = count_in + 1;
  37           if (count_in >= 6) full_in = 1;
  38       end
  39     end else begin
  40       if (full_in) begin
  41         `onwrite(horn_in_r, horn_in_a)
  42           full_in = 0;
  43           count_in = 0;
  44         end
  45       end
  46     end
  47   end
  48
  49   always @(posedge clk) begin
  50     if (!full_out) begin
  51       `onread(funnel_out_r, funnel_out_a)
  52           full_out = 1;
  53           count_out = 6;
  54           out_d = funnel_out_d;
  55       end
  56     end else begin
  57       `onwrite(out_r, out_a)
  58         if (count_out<6) out_d = out_d >> 8;
  59         count_out = count_out - 1;
  60         if (count_out==0) full_out = 0;
  61       end
  62     end
  63   end
  64
  65 endmodule