testCode/header.hsp

   1 ********************** TSMC 90nm Header **************************
   2
   3 ******************************************************************
   4 * Set Process, Voltage and Temperature corner
   5 ******************************************************************
   6
   7 .protect
   8 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT
   9 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_RES
  10 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_18
  11 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_na18
  12 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_esd
  13 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_18
  14 .unprotect
  15
  16 .param sup=0.9    * Supply voltage
  17 .temp 80          * Temperature
  18
  19 ******************************************************************
  20 * Standard Parameters and Options
  21 ******************************************************************
  22
  23 .param vsupply=sup
  24 .param vhi=sup
  25 .param vlo=0
  26 .param strong0=0 * Used in verilog, just needs to be defined to run hspice
  27 .param strong1=1 * Used in verilog, just needs to be defined to run hspice
  28 vvdd vdd gnd 'sup'
  29 .options ACCT OPTS post
  30 *.option post probe
  31 .opt scale=0.05u
  32 .op
  33
  34 .param AVT0N = AGAUSS(0.0,  '0.01 / 0.1' , 1)
  35 .param AVT0P = AGAUSS(0.0,  '0.01 / 0.1' , 1)
  36 .param ABN = AGAUSS(0.0,  '0.02 / 0.1' , 1)
  37 .param ABP = AGAUSS(0.0,  '0.02 / 0.1' , 1)
  38
  39 ******************************************************************
  40 * hsim gunk
  41 ******************************************************************
  42 .hsimparam HSIMDCINIT=0
  43 .hsimparam HSIMVDD=0.9
  44 .param HSIMSTOPAT=0
  45 .param HSIMOUTPUT=fsdb
  46 .param HSIMOUTPUTTBL=rawfile