1 --- gcc/config/mips/mips.md Thu Aug 21 12:04:35 2003
2 +++ gcc/config/mips/mips.md Thu Aug 21 12:05:59 2003
3 @@ -4843,155 +4843,6 @@
4 ;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
5 ;; It isn't clear whether this will give better code.
7 -;; Only specify the mode operand 1, the rest are assumed to be word_mode.
9 - [(set (match_operand 0 "register_operand" "")
10 - (sign_extract (match_operand:QI 1 "memory_operand" "")
11 - (match_operand 2 "immediate_operand" "")
12 - (match_operand 3 "immediate_operand" "")))]
16 - /* If the field does not start on a byte boundary, then fail. */
17 - if (INTVAL (operands[3]) % 8 != 0)
20 - /* MIPS I and MIPS II can only handle a 32bit field. */
21 - if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
24 - /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
26 - && INTVAL (operands[2]) != 64
27 - && INTVAL (operands[2]) != 32)
30 - /* This can happen for a 64 bit target, when extracting a value from
31 - a 64 bit union member. extract_bit_field doesn't verify that our
32 - source matches the predicate, so we force it to be a MEM here. */
33 - if (GET_CODE (operands[1]) != MEM)
36 - /* Change the mode to BLKmode for aliasing purposes. */
37 - operands[1] = adjust_address (operands[1], BLKmode, 0);
38 - set_mem_size (operands[1], GEN_INT (INTVAL (operands[2]) / BITS_PER_UNIT));
40 - /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value. */
41 - if (INTVAL (operands[2]) == 64)
42 - emit_insn (gen_movdi_uld (operands[0], operands[1]));
47 - operands[0] = gen_lowpart (SImode, operands[0]);
48 - if (operands[0] == NULL_RTX)
51 - emit_insn (gen_movsi_ulw (operands[0], operands[1]));
56 -;; Only specify the mode operand 1, the rest are assumed to be word_mode.
57 -(define_expand "extzv"
58 - [(set (match_operand 0 "register_operand" "")
59 - (zero_extract (match_operand:QI 1 "memory_operand" "")
60 - (match_operand 2 "immediate_operand" "")
61 - (match_operand 3 "immediate_operand" "")))]
65 - /* If the field does not start on a byte boundary, then fail. */
66 - if (INTVAL (operands[3]) % 8 != 0)
69 - /* MIPS I and MIPS II can only handle a 32bit field. */
70 - if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
73 - /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
75 - && INTVAL (operands[2]) != 64
76 - && INTVAL (operands[2]) != 32)
79 - /* This can happen for a 64 bit target, when extracting a value from
80 - a 64 bit union member. extract_bit_field doesn't verify that our
81 - source matches the predicate, so we force it to be a MEM here. */
82 - if (GET_CODE (operands[1]) != MEM)
85 - /* Change the mode to BLKmode for aliasing purposes. */
86 - operands[1] = adjust_address (operands[1], BLKmode, 0);
87 - set_mem_size (operands[1], GEN_INT (INTVAL (operands[2]) / BITS_PER_UNIT));
89 - /* Otherwise, emit a lwl/lwr pair to load the value. */
90 - if (INTVAL (operands[2]) == 64)
91 - emit_insn (gen_movdi_uld (operands[0], operands[1]));
96 - operands[0] = gen_lowpart (SImode, operands[0]);
97 - if (operands[0] == NULL_RTX)
100 - emit_insn (gen_movsi_ulw (operands[0], operands[1]));
105 -;; Only specify the mode operands 0, the rest are assumed to be word_mode.
106 -(define_expand "insv"
107 - [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
108 - (match_operand 1 "immediate_operand" "")
109 - (match_operand 2 "immediate_operand" ""))
110 - (match_operand 3 "register_operand" ""))]
114 - /* If the field does not start on a byte boundary, then fail. */
115 - if (INTVAL (operands[2]) % 8 != 0)
118 - /* MIPS I and MIPS II can only handle a 32bit field. */
119 - if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
122 - /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
124 - && INTVAL (operands[1]) != 64
125 - && INTVAL (operands[1]) != 32)
128 - /* This can happen for a 64 bit target, when storing into a 32 bit union
129 - member. store_bit_field doesn't verify that our target matches the
130 - predicate, so we force it to be a MEM here. */
131 - if (GET_CODE (operands[0]) != MEM)
134 - /* Change the mode to BLKmode for aliasing purposes. */
135 - operands[0] = adjust_address (operands[0], BLKmode, 0);
136 - set_mem_size (operands[0], GEN_INT (INTVAL (operands[1]) / BITS_PER_UNIT));
138 - /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value. */
139 - if (INTVAL (operands[1]) == 64)
140 - emit_insn (gen_movdi_usd (operands[0], operands[3]));
145 - operands[3] = gen_lowpart (SImode, operands[3]);
146 - if (operands[3] == NULL_RTX)
149 - emit_insn (gen_movsi_usw (operands[0], operands[3]));
154 -;; unaligned word moves generated by the bit field patterns
156 (define_insn "movsi_ulw"
157 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
158 (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")]
159 --- gcc/config/mips/mips.c Fri Jan 31 15:51:23 2003
160 +++ gcc/config/mips/mips.c Thu Aug 21 20:04:19 2003
161 @@ -4027,34 +4027,6 @@
165 - /* ??? Fails because of a MIPS assembler bug? */
166 - else if (TARGET_64BIT && bytes >= 8
168 - && ! TARGET_MIPS16)
170 - if (BYTES_BIG_ENDIAN)
172 - load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
173 - load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
174 - load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
175 - load_store[num].last_store = "sdr\t%0,%2";
176 - load_store[num].final = "sdl\t%0,%1";
180 - load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
181 - load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
182 - load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
183 - load_store[num].last_store = "sdr\t%0,%1";
184 - load_store[num].final = "sdl\t%0,%2";
187 - load_store[num].mode = DImode;
193 else if (bytes >= 4 && align >= 4)
195 load_store[num].load = "lw\t%0,%1";
196 @@ -4065,33 +4037,6 @@
197 load_store[num].mode = SImode;
202 - else if (bytes >= 4
204 - && ! TARGET_MIPS16)
206 - if (BYTES_BIG_ENDIAN)
208 - load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
209 - load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
210 - load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
211 - load_store[num].last_store = "swr\t%0,%2";
212 - load_store[num].final = "swl\t%0,%1";
216 - load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
217 - load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
218 - load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
219 - load_store[num].last_store = "swr\t%0,%1";
220 - load_store[num].final = "swl\t%0,%2";
223 - load_store[num].mode = SImode;
229 else if (bytes >= 2 && align >= 2)