+host = intel2950-5.eecs.berkeley.edu
+remote_ise = /tools/xilinx/ISE9.1i_lin
+remote_edk = /tools/xilinx/EDK9.1i
+remote_dir = /scratch/megacz/fleet/
+
+#host = mm2.millennium.berkeley.edu
+#remote_ise = /scratch/megacz/xilinx/ise/
+#remote_edk = /scratch/megacz/xilinx/edk/
+#remote_dir = /scratch/megacz/fleet/
+
+
+xilinx = cd build/fpga;
+xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(remote_ise)/bin/lin:$(remote_edk)/bin/lin
+xilinx += PATH=$$PATH:$(remote_ise)/bin/lin:$(remote_edk)/bin/lin
+xilinx += XST_VERSION=9.2i
+xilinx += XILINX=$(remote_ise)
+xilinx += XIL_XST_HIDEMESSAGES=hdl_and_low_levels
+xilinx += XILINX_EDK=$(remote_edk)
+
+xilinx_ise = $(xilinx) $(remote_ise)/bin/lin/
+xilinx_edk = $(xilinx) $(remote_edk)/bin/lin/
+
+speed_grade = 11
+device = xc4vfx60ff1152-${speed_grade}
+#device = xc2vp70-7ff1704
+
+upload: fleet.jar build/fpga/main.bit
+ mkdir -p build
+ chmod +x misc/program.sh
+ rsync -are ssh --progress --verbose ./ root@goliath:fleet/
+
+build/fpga/main.bit: $(java_files) $(ship_files)
+ make fleet.jar
+ mkdir -p build/fpga
+ $(java) $(cp) edu.berkeley.fleet.fpga.Fpga build/fpga/
+ cp src/edu/berkeley/fleet/fpga/* build/fpga || true
+ for A in `find ships -name \*.ship`;\
+ do java -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\
+ done
+ rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
+ time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_ise} remote_ise=${remote_ise} remote_edk=${remote_edk}'
+ scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/
+
+pcore = ${remote_edk}/hw/XilinxProcessorIPLib/pcores
+synth:
+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
+ rm -f build/fpga/main.lso
+ echo work >> build/fpga/main.lso
+ rm -f build/fpga/main.prj
+ cd build/fpga; for A in *.v; do echo verilog work \""$$A"\"; done >> main.prj
+ cd build/fpga; touch main.ini
+ cd build/fpga; mkdir -p tmp
+ cd build/fpga; mkdir -p xst
+ rm -rf build/fpga/_ngo
+ skill xst_original
+
+ rm -f build/fpga/main.xst
+ echo "set -tmpdir ./tmp" >> build/fpga/main.xst
+ echo "set -xsthdpdir ./xst" >> build/fpga/main.xst
+ echo "set -xsthdpini main.ini" >> build/fpga/main.xst
+ echo -n "run" >> build/fpga/main.xst
+ echo -n " -ifn main.prj" >> build/fpga/main.xst
+ echo -n " -ifmt mixed" >> build/fpga/main.xst
+ echo -n " -ofn main" >> build/fpga/main.xst
+ echo -n " -ofmt NGC" >> build/fpga/main.xst
+ echo -n " -p xc4vfx60-11ff1152" >> build/fpga/main.xst
+ echo -n " -top main" >> build/fpga/main.xst
+ echo -n " -opt_mode area" >> build/fpga/main.xst
+ echo -n " -opt_level 2" >> build/fpga/main.xst
+ echo -n " -iuc NO" >> build/fpga/main.xst
+ echo -n " -lso main.lso" >> build/fpga/main.xst
+ echo -n " -keep_hierarchy NO" >> build/fpga/main.xst
+ echo -n " -rtlview Yes" >> build/fpga/main.xst
+ echo -n " -glob_opt AllClockNets" >> build/fpga/main.xst
+ echo -n " -read_cores YES" >> build/fpga/main.xst
+ echo -n " -write_timing_constraints NO" >> build/fpga/main.xst
+ echo -n " -cross_clock_analysis YES" >> build/fpga/main.xst
+ echo -n " -hierarchy_separator /" >> build/fpga/main.xst
+ echo -n " -bus_delimiter <>" >> build/fpga/main.xst
+ echo -n " -case maintain" >> build/fpga/main.xst
+ echo -n " -slice_utilization_ratio 100" >> build/fpga/main.xst
+ echo -n " -verilog2001 YES" >> build/fpga/main.xst
+ echo -n " -fsm_extract Yes" >> build/fpga/main.xst
+ echo -n " -fsm_encoding Auto" >> build/fpga/main.xst
+ echo -n " -safe_implementation No" >> build/fpga/main.xst
+ echo -n " -fsm_style lut" >> build/fpga/main.xst
+ echo -n " -ram_extract Yes" >> build/fpga/main.xst
+ echo -n " -ram_style Auto" >> build/fpga/main.xst
+ echo -n " -rom_extract Yes" >> build/fpga/main.xst
+ echo -n " -mux_style Auto" >> build/fpga/main.xst
+ echo -n " -decoder_extract YES" >> build/fpga/main.xst
+ echo -n " -priority_extract YES" >> build/fpga/main.xst
+ echo -n " -shreg_extract YES" >> build/fpga/main.xst
+ echo -n " -shift_extract YES" >> build/fpga/main.xst
+ echo -n " -xor_collapse YES" >> build/fpga/main.xst
+ echo -n " -rom_style Auto" >> build/fpga/main.xst
+ echo -n " -mux_extract YES" >> build/fpga/main.xst
+ echo -n " -resource_sharing YES" >> build/fpga/main.xst
+ echo -n " -mult_style auto" >> build/fpga/main.xst
+ echo -n " -iobuf YES" >> build/fpga/main.xst
+ echo -n " -max_fanout 10000" >> build/fpga/main.xst
+ echo -n " -bufg 1" >> build/fpga/main.xst
+ echo -n " -register_duplication YES" >> build/fpga/main.xst
+ echo -n " -register_balancing Yes" >> build/fpga/main.xst
+ echo -n " -slice_packing Yes" >> build/fpga/main.xst
+ echo -n " -optimize_primitives Yes" >> build/fpga/main.xst
+ echo -n " -tristate2logic Yes" >> build/fpga/main.xst
+ echo -n " -use_clock_enable Yes" >> build/fpga/main.xst
+ echo -n " -use_sync_set Yes" >> build/fpga/main.xst
+ echo -n " -use_sync_reset Yes" >> build/fpga/main.xst
+ echo -n " -iob auto" >> build/fpga/main.xst
+ echo -n " -equivalent_register_removal YES" >> build/fpga/main.xst
+ echo -n " -slice_utilization_ratio_maxmargin 5" >> build/fpga/main.xst
+ echo >> build/fpga/main.xst
+
+ rm -f build/fpga/main.ut
+ echo '-w' >> build/fpga/main.ut
+ echo '-g CclkPin:PULLUP' >> build/fpga/main.ut
+ echo '-g TdoPin:PULLNONE' >> build/fpga/main.ut
+ echo '-g M1Pin:PULLDOWN' >> build/fpga/main.ut
+ echo '-g DonePin:PULLUP' >> build/fpga/main.ut
+ echo '-g DriveDone:No' >> build/fpga/main.ut
+ echo '-g StartUpClk:JTAGCLK' >> build/fpga/main.ut
+ echo '-g DONE_cycle:4' >> build/fpga/main.ut
+ echo '-g GTS_cycle:5' >> build/fpga/main.ut
+ echo '-g M0Pin:PULLUP' >> build/fpga/main.ut
+ echo '-g M2Pin:PULLUP' >> build/fpga/main.ut
+ echo '-g ProgPin:PULLUP' >> build/fpga/main.ut
+ echo '-g TckPin:PULLUP' >> build/fpga/main.ut
+ echo '-g TdiPin:PULLUP' >> build/fpga/main.ut
+ echo '-g TmsPin:PULLUP' >> build/fpga/main.ut
+ echo '-g DonePipe:No' >> build/fpga/main.ut
+ echo '-g GWE_cycle:6' >> build/fpga/main.ut
+ echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
+ echo '-g Security:NONE' >> build/fpga/main.ut
+ echo '-g Persist:No' >> build/fpga/main.ut
+
+ $(xilinx_ise)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
+ $(xilinx_ise)ngdbuild -aul -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
+ $(xilinx_ise)map -cm area -intstyle xflow -p $(device) -pr b -ol high -o main_map.ncd main.ngd main.pcf
+ $(xilinx_ise)par -w -intstyle xflow -t 99 -pl high -rl high main_map.ncd main.ncd main.pcf
+ $(xilinx_ise)bitgen -intstyle xflow -f main.ut main.ncd
+# $(xilinx_ise)trce -intstyle xflow -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
+ $(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ml410 -ace mainx.ace
+ mv build/fpga/mainx.ace build/fpga/main.ace # genace throws a fit if the filename prefix is the same?
+
+
+runserver: fleet.jar
+ java -Djava.library.path=lib -cp fleet.jar:lib/RXTXcomm.jar edu.berkeley.fleet.fpga.Server
+
+test: fleet.jar; $(java) -jar fleet.jar test ships/*.ship tests
+testfpga: fleet.jar; $(java) -jar fleet.jar target=fpga test ships/*.ship tests
+
+## Manual ####################################################################################
+
+svgs = $(shell find doc -name \*.svg)
+%.eps: %.svg
+ DISPLAY= /Applications/Inkscape.app/Contents//Resources/bin/inkscape -z --export-area-drawing $^ --export-eps=$@
+
+%.pdf: %.eps
+ epstopdf $^ --outfile=$@
+
+manual: archmanual toolmanual
+
+archmanual: fleet.jar $(svgs:%.svg=%.pdf)
+ $(java) -jar fleet.jar doc
+ cd .tmp; ln -sf ../doc/*.bib .
+ cd .tmp; TEXINPUTS=$$TEXINPUTS:../src/edu/berkeley/fleet/assembler/:../doc/ pdflatex FleetTwo.Manual.tex
+ cd .tmp; for A in *.mp; do mpost --tex=latex $$A; done
+ cd .tmp; TEXINPUTS=$$TEXINPUTS:../src/edu/berkeley/fleet/assembler/:../doc/ pdflatex FleetTwo.Manual.tex
+ open .tmp/FleetTwo.Manual.pdf
+toolmanual: fleet.jar $(svgs:%.svg=%.pdf)
+ $(java) -jar fleet.jar doc
+ cd .tmp; ln -sf ../doc/*.bib .
+ cd .tmp; TEXINPUTS=$$TEXINPUTS:../src/edu/berkeley/fleet/assembler/:../doc/ pdflatex toolchain.tex
+ open .tmp/toolchain.pdf
+
+## API docs ####################################################################################