+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/ddr2/* .
+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/dvi/* .
+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/zbt/* .
+ rm -f build/fpga/main.lso
+ echo work >> build/fpga/main.lso
+ rm -f build/fpga/main.prj
+ cd build/fpga; for A in *.v; do echo verilog work \""$$A"\"; done >> main.prj
+ cd build/fpga; for A in *.vhd; do echo vhdl work \""$$A"\"; done >> main.prj
+ cd build/fpga; touch main.ini
+ cd build/fpga; mkdir -p tmp
+ cd build/fpga; mkdir -p xst
+ rm -rf build/fpga/_ngo
+ skill xst_original
+
+ rm -f build/fpga/main.xst
+ echo "set -tmpdir ./tmp" >> build/fpga/main.xst
+ echo "set -xsthdpdir ./xst" >> build/fpga/main.xst
+ echo "set -xsthdpini main.ini" >> build/fpga/main.xst
+ echo -n "run" >> build/fpga/main.xst
+ echo -n " -ifn main.prj" >> build/fpga/main.xst
+ echo -n " -ifmt mixed" >> build/fpga/main.xst
+ echo -n " -ofn main" >> build/fpga/main.xst
+ echo -n " -ofmt NGC" >> build/fpga/main.xst
+ echo -n " -p ${device}" >> build/fpga/main.xst
+ echo -n " -top main" >> build/fpga/main.xst
+ echo -n " -opt_mode ${opt_for}" >> build/fpga/main.xst
+ echo -n " -opt_level 2" >> build/fpga/main.xst
+ echo -n " -iuc NO" >> build/fpga/main.xst
+ echo -n " -lso main.lso" >> build/fpga/main.xst
+ echo -n " -keep_hierarchy NO" >> build/fpga/main.xst
+ echo -n " -rtlview Yes" >> build/fpga/main.xst
+ echo -n " -glob_opt AllClockNets" >> build/fpga/main.xst
+ echo -n " -read_cores YES" >> build/fpga/main.xst
+ echo -n " -write_timing_constraints NO" >> build/fpga/main.xst
+ echo -n " -cross_clock_analysis YES" >> build/fpga/main.xst
+ echo -n " -hierarchy_separator /" >> build/fpga/main.xst
+ echo -n " -bus_delimiter <>" >> build/fpga/main.xst
+ echo -n " -case maintain" >> build/fpga/main.xst
+ echo -n " -slice_utilization_ratio 100" >> build/fpga/main.xst
+ echo -n " -verilog2001 YES" >> build/fpga/main.xst
+ echo -n " -fsm_extract Yes" >> build/fpga/main.xst
+ echo -n " -fsm_encoding Auto" >> build/fpga/main.xst
+ echo -n " -safe_implementation No" >> build/fpga/main.xst
+ echo -n " -fsm_style lut" >> build/fpga/main.xst
+ echo -n " -ram_extract Yes" >> build/fpga/main.xst
+ echo -n " -ram_style Auto" >> build/fpga/main.xst
+ echo -n " -rom_extract Yes" >> build/fpga/main.xst
+ echo -n " -mux_style Auto" >> build/fpga/main.xst
+ echo -n " -decoder_extract YES" >> build/fpga/main.xst
+ echo -n " -priority_extract YES" >> build/fpga/main.xst
+ echo -n " -shreg_extract YES" >> build/fpga/main.xst
+ echo -n " -shift_extract YES" >> build/fpga/main.xst
+ echo -n " -xor_collapse YES" >> build/fpga/main.xst
+ echo -n " -rom_style Auto" >> build/fpga/main.xst
+ echo -n " -mux_extract YES" >> build/fpga/main.xst
+ echo -n " -resource_sharing YES" >> build/fpga/main.xst
+ echo -n " -mult_style auto" >> build/fpga/main.xst
+ echo -n " -iobuf YES" >> build/fpga/main.xst
+ echo -n " -max_fanout 10000" >> build/fpga/main.xst
+ echo -n " -bufg 1" >> build/fpga/main.xst
+ echo -n " -register_duplication YES" >> build/fpga/main.xst
+ echo -n " -register_balancing Yes" >> build/fpga/main.xst
+ echo -n " -slice_packing Yes" >> build/fpga/main.xst
+ echo -n " -optimize_primitives Yes" >> build/fpga/main.xst
+ echo -n " -tristate2logic Yes" >> build/fpga/main.xst
+ echo -n " -use_clock_enable Yes" >> build/fpga/main.xst
+ echo -n " -use_sync_set Yes" >> build/fpga/main.xst
+ echo -n " -use_sync_reset Yes" >> build/fpga/main.xst
+ echo -n " -iob auto" >> build/fpga/main.xst
+ echo -n " -equivalent_register_removal YES" >> build/fpga/main.xst
+ echo -n " -slice_utilization_ratio_maxmargin 5" >> build/fpga/main.xst
+ echo >> build/fpga/main.xst
+
+ rm -f build/fpga/main.ut
+ echo '-w' >> build/fpga/main.ut
+ echo '-g CclkPin:PULLUP' >> build/fpga/main.ut
+ echo '-g TdoPin:PULLNONE' >> build/fpga/main.ut
+ echo '-g M1Pin:PULLDOWN' >> build/fpga/main.ut
+ echo '-g DonePin:PULLUP' >> build/fpga/main.ut
+ echo '-g DriveDone:No' >> build/fpga/main.ut
+ echo '-g StartUpClk:JTAGCLK' >> build/fpga/main.ut
+ echo '-g DONE_cycle:4' >> build/fpga/main.ut
+ echo '-g GTS_cycle:5' >> build/fpga/main.ut
+ echo '-g M0Pin:PULLUP' >> build/fpga/main.ut
+ echo '-g M2Pin:PULLUP' >> build/fpga/main.ut
+ echo '-g ProgPin:PULLUP' >> build/fpga/main.ut
+ echo '-g TckPin:PULLUP' >> build/fpga/main.ut
+ echo '-g TdiPin:PULLUP' >> build/fpga/main.ut
+ echo '-g TmsPin:PULLUP' >> build/fpga/main.ut
+ echo '-g DonePipe:No' >> build/fpga/main.ut
+ echo '-g GWE_cycle:6' >> build/fpga/main.ut
+ echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
+ echo '-g Security:NONE' >> build/fpga/main.ut
+ echo '-g Persist:No' >> build/fpga/main.ut
+
+ $(xilinx_ise)xst ${intstyle} -ifn main.xst -ofn main.syr < main.xst \
+ | grep --line-buffered -v 'been backward balanced into' \
+ | grep --line-buffered -v 'IDDR has been replaced by IDDR_2CLK' \
+ | grep --line-buffered -v 'WARNING:Xst:616 - Invalid property'
+ cat build/fpga/*.ucf > build/fpga/main.ucf
+ $(xilinx_ise)ngdbuild ${intstyle} -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
+ $(xilinx_ise)map ${intstyle} -ol ${effort} -p $(device) -pr b -cm ${opt_for} -o main_map.ncd main.ngd main.pcf
+ $(xilinx_ise)par ${intstyle} -pl ${effort} -ol ${effort} -w main_map.ncd main.ncd main.pcf
+ $(xilinx_ise)trce ${intstyle} -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
+ $(xilinx_ise)bitgen ${intstyle} -f main.ut main.ncd
+ $(xilinx) tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
+ mv build/fpga/mainx.ace build/fpga/main.ace # genace throws a fit if the filename prefix is the same?
+
+
+runserver: fleet.jar
+ java -Djava.library.path=lib -cp fleet.jar:lib/RXTXcomm.jar edu.berkeley.fleet.fpga.Server
+
+test: fleet.jar
+ $(java) -jar fleet.jar test ships/*.ship tests
+ java -cp fleet.jar edu.berkeley.fleet.dataflow.MergeSort interpreter Memory 0 256
+testfpga: fleet.jar
+ $(java) -jar fleet.jar target=fpga test ships/*.ship tests
+ java -cp fleet.jar edu.berkeley.fleet.dataflow.MergeSort fpga Memory 0 256