add Dvi.ship

[fleet.git] / ships / Debug.ship

diff --git a/ships/Debug.ship b/ships/Debug.ship
index c8e102e..0fbb9e0 100644 (file)
--- a/ships/Debug.ship
+++ b/ships/Debug.ship
@@ -1,12 +1,21 @@
 ship: Debug
 
 == Ports ===========================================================
 ship: Debug
 
 == Ports ===========================================================

-data  in:   in
+data  in:     in
+dockless out: out
+
+percolate down: uart_in     1
+percolate up:   uart_out    1
+percolate up:   rst_out     1
+percolate down: rst_in      1

 
 == Constants ========================================================
 
 == TeX ==============================================================
 
 
 == Constants ========================================================
 
 == TeX ==============================================================
 

+percolate up:   uart_rts    1
+percolate down: uart_cts    1
+

 This ship is used for debugging.  It has only one port, {\tt in}.
 Programmers should send debug report values to this port.  How such
 values are reported back to the programmer doing the debugging is left
 This ship is used for debugging.  It has only one port, {\tt in}.
 Programmers should send debug report values to this port.  How such
 values are reported back to the programmer doing the debugging is left

@@ -30,25 +39,104 @@ public void service() {
 
 == FPGA ==============================================================
 
 
 == FPGA ==============================================================
 

-module debug (clk, rst,
-              data_debug_data_r, data_debug_data_a, data_debug_data,
-              data_debug_out_r, data_debug_out_a, data_debug_out );
-  input clk;
-  input rst;
-
-  input  data_debug_data_r;
-  output data_debug_data_a;
-  input  [`DATAWIDTH:0] data_debug_data;
-
-  output  data_debug_out_r;
-  input   data_debug_out_a;
-  output  [`DATAWIDTH:0] data_debug_out;
-
-  assign  data_debug_out_r  = data_debug_data_r;
-  assign  data_debug_data_a = data_debug_out_a;
-  assign  data_debug_out    = data_debug_data;
-
-endmodule
+  wire break_i;
+  reg break_last;
+  reg send_k;
+  initial send_k = 0;
+
+  reg [`WORDWIDTH-1:0] data_to_host_full_word;
+  reg [7:0] count_in;
+  reg [7:0] count_out;
+  reg [49:0] out_d;
+  assign out_d_ = out_d;
+
+  wire       data_to_host_full;
+  reg  [7:0] data_to_host;
+  wire       data_to_fleet_empty;
+  wire [7:0] data_to_fleet;
+  reg        data_to_host_write_enable;
+  reg        data_to_fleet_read_enable;
+
+  wire sio_ce;
+  wire sio_ce_x4;
+
+  wire break;
+  wire uart_cts;
+  assign uart_cts = 0;
+  assign rst_out = rst_in || break;
+
+  // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
+  // using a 33Mhz clock,
+  //   33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1
+  sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
+  sasc_top sasc_top(clk, !rst_in,
+                    uart_in,
+                    uart_out,
+                    uart_cts,
+                    uart_rts, 
+                    sio_ce,
+                    sio_ce_x4,
+                    data_to_host,
+                    data_to_fleet,
+                    data_to_fleet_read_enable,
+                    data_to_host_write_enable,
+                    data_to_host_full,
+                    data_to_fleet_empty,
+                    break,
+                    break_i);
+
+   // break and break are _active high_
+   always @(posedge clk) break_last <= break;
+   assign break_i    =  break && !break_last;
+   assign break_done = !break &&  break_last;
+
+   // fpga -> host
+   always @(posedge clk) begin
+     if (rst) begin
+       count_in  <= 0;
+       count_out <= 0;
+       `reset
+     end else begin
+
+       `cleanup
+
+       // fpga -> host
+       data_to_host_write_enable <= 0;
+       if (break_i) begin
+       end else if (break_done) begin
+         data_to_host_write_enable <= 1;
+         data_to_host <= 111;
+         send_k <= 1;
+       end else if (send_k) begin
+         data_to_host_write_enable <= 1;
+         data_to_host <= 107;
+         send_k <= 0;
+       end else if (count_out==0 && `in_full) begin
+         `drain_in
+         data_to_host_full_word <= in_d;
+         count_out <= 8;
+       end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable) begin
+         data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
+         data_to_host_full_word <= (data_to_host_full_word >> 6);
+         data_to_host_write_enable <= 1;
+         count_out <= count_out-1;
+       end
+
+       // host -> fpga
+       data_to_fleet_read_enable <= 0;
+       if (!data_to_fleet_empty && `out_empty && !data_to_fleet_read_enable) begin
+         out_d <= { out_d[43:0], data_to_fleet[5:0] };
+         data_to_fleet_read_enable <= 1;
+         if (count_in==9) begin
+           count_in <= 0;
+           `fill_out
+         end else begin
+           count_in <= count_in+1;
+         end
+       end
+
+    end
+  end

 
 == Test ================================================================
 #expect 25
 
 == Test ================================================================
 #expect 25