+== FPGA:Bee2 ==============================================================
+
+ wire CCLK_int;
+
+ wire [0:7] D_I;
+ wire [0:7] D_O;
+ wire [0:7] D_T;
+
+ wire User_Rst;
+
+ wire [7:0] write_data;
+ wire write_enable;
+ wire write_full;
+
+ wire [7:0] read_data;
+ wire read_empty;
+ wire read_enable;
+
+ // IO buffers
+ OBUF obuf_cclk( .I( CCLK_int ), .O( CCLK ) );
+ IOBUF iobuf_d0( .I( D_O[0] ), .IO( D[0] ), .O( D_I[0] ), .T( D_T[0] ) );
+ IOBUF iobuf_d1( .I( D_O[1] ), .IO( D[1] ), .O( D_I[1] ), .T( D_T[1] ) );
+ IOBUF iobuf_d2( .I( D_O[2] ), .IO( D[2] ), .O( D_I[2] ), .T( D_T[2] ) );
+ IOBUF iobuf_d3( .I( D_O[3] ), .IO( D[3] ), .O( D_I[3] ), .T( D_T[3] ) );
+ IOBUF iobuf_d4( .I( D_O[4] ), .IO( D[4] ), .O( D_I[4] ), .T( D_T[4] ) );
+ IOBUF iobuf_d5( .I( D_O[5] ), .IO( D[5] ), .O( D_I[5] ), .T( D_T[5] ) );
+ IOBUF iobuf_d6( .I( D_O[6] ), .IO( D[6] ), .O( D_I[6] ), .T( D_T[6] ) );
+ IOBUF iobuf_d7( .I( D_O[7] ), .IO( D[7] ), .O( D_I[7] ), .T( D_T[7] ) );
+
+ // Clock buffer and reset
+ wire clk_fast;
+ wire clk_half;
+ wire clk_fb;
+ IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ), .IB( Clkin_m ), .O( clk_fast ) );
+
+ wire clkdiv0_unbuffered;
+ wire clk0_unbuffered;
+ wire clk0_fb;
+// BUFG bufg1 (.I(clkdiv0_unbuffered), .O(clk_out));
+// BUFG bufg1 (.I(clk_fast), .O(clk_out));
+// BUFG bufg1 (.I(clk0_unbuffered), .O(clk_out));
+ BUFG bufg2 (.I(clk0_unbuffered), .O(clk0_fb));
+
+
+reg foo;
+reg foo2;
+ BUFG bufg1 (.I(foo2), .O(clk_out));
+
+always @(posedge clk_fast) begin
+ if (foo)
+ foo2 <= ~foo2;
+ foo <= ~foo;
+end
+
+ DCM
+ #(
+ .CLKIN_PERIOD (10.0),
+ .DUTY_CYCLE_CORRECTION ("TRUE"),
+ .DLL_FREQUENCY_MODE ("LOW"),
+ .STARTUP_WAIT ("FALSE")
+ ) ddr2_dcm (
+ .CLKIN (clk_fast),
+ .CLKFB (clk0_fb),
+ .CLK0 (clk0_unbuffered),
+ .RST (User_Rst)
+ );
+
+// BUFG GBUF_FOR_MUX_CLOCK (.I(clk_half), .O(clk_out));
+// BUFG GBUF_FOR_MUX_CLOCK (.I(clk_fast), .O(clk_out));
+
+
+ wire [0:3] rstr;
+ FD rstr0( .D( 1'b0 ), .Q( rstr[0] ), .C( clk ) ); defparam rstr0.INIT = 1'b1;
+ FD rstr1( .D( rstr[0] ), .Q( rstr[1] ), .C( clk ) ); defparam rstr1.INIT = 1'b1;
+ FD rstr2( .D( rstr[1] ), .Q( rstr[2] ), .C( clk ) ); defparam rstr2.INIT = 1'b1;
+ FD rstr3( .D( rstr[2] ), .Q( rstr[3] ), .C( clk ) ); defparam rstr3.INIT = 1'b1;
+ assign User_Rst = |rstr;
+
+ user_fifo test_fifo(
+ .WrFifo_Din( write_data ),
+ .WrFifo_WrEn( write_enable ),
+ .WrFifo_Full( write_full ),
+ .WrFifo_WrCnt( ),
+ .RdFifo_Dout( read_data ),
+ .RdFifo_RdEn( read_enable ),
+ .RdFifo_Empty( read_empty ),
+ .RdFifo_RdCnt( ),
+ .User_Rst( User_Rst ),
+ .User_Clk( clk ),
+ .Sys_Rst( User_Rst ),
+ .Sys_Clk( clk_fast ),
+ .D_I( D_I ),
+ .D_O( D_O ),
+ .D_T( D_T ),
+ .RDWR_B( RDWR_B ),
+ .CS_B( CS_B ),
+ .INIT_B( INIT_B ),
+ .CCLK( CCLK_int )
+ );
+
+ wire data_to_host_full;
+ reg [7:0] data_to_host;
+ wire data_to_fleet_empty;
+ wire [7:0] data_to_fleet;
+ reg data_to_host_write_enable;
+ reg data_to_fleet_read_enable;
+
+ assign data_to_fleet = read_data;
+ assign read_enable = data_to_fleet_read_enable;
+ assign write_enable = data_to_host_write_enable;
+ assign write_data = data_to_host;
+ assign data_to_fleet_empty = read_empty;
+ assign data_to_host_full = write_full;
+
+ initial data_to_fleet_read_enable = 1;
+ initial data_to_host_write_enable = 0;
+
+ reg [7:0] force_reset;
+ assign rst_out = User_Rst || (force_reset!=0);
+
+ /// Common //////////////////////////////////////////////////////////////////////////////
+
+ reg send_k;
+ initial send_k = 0;
+
+ reg [`WORDWIDTH-1:0] data_to_host_full_word;
+ reg [7:0] count_in;
+ reg [7:0] count_out;
+ reg [49:0] out_d;
+ assign out_d_ = out_d;
+
+ reg [16:0] credits;
+
+ // fpga -> host
+ always @(posedge clk) begin
+ if (/*rst_in*/User_Rst) begin
+ count_in <= 0;
+ count_out <= 0;
+ force_reset <= 0;
+ credits = 0;
+ `reset
+ end else begin