- reg write_flag;
- reg [(`BRAM_ADDR_WIDTH-1):0] cursor;
- wire [(`BRAM_ADDR_WIDTH-1):0] addr1;
-
- // bram //////////////////////////////////////////////////////////////////////////////
-`define BRAM_ADDR_WIDTH 14
-`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))
-
- reg [(`WORDWIDTH-1):0] ram [((`BRAM_SIZE)-1):0];
- reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
- reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
- always @(posedge clk) begin
- if (write_flag)
- ram[addr1] <= inDataWrite_d;
- read_a <= addr1;
- read_dpra <= cursor;
- end