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relocate InstructionEncoder to FleetTwoFleet and make it a subclass of Fleet
[fleet.git]
/
src
/
edu
/
berkeley
/
fleet
/
fpga
/
sasc_top.v
diff --git
a/src/edu/berkeley/fleet/fpga/sasc_top.v
b/src/edu/berkeley/fleet/fpga/sasc_top.v
index
1ebb15a
..
a5dfa77
100644
(file)
--- a/
src/edu/berkeley/fleet/fpga/sasc_top.v
+++ b/
src/edu/berkeley/fleet/fpga/sasc_top.v
@@
-90,7
+90,7
@@
module sasc_top( clk, rst,
// Internal Interface
din_i, dout_o, re_i, we_i, full_o, empty_o,
// Internal Interface
din_i, dout_o, re_i, we_i, full_o, empty_o,
- break_o);
+ break_o, flush_i);
input clk;
input rst;
input clk;
input rst;
@@
-99,6
+99,7
@@
output txd_o;
input cts_i;
output rts_o;
output break_o;
input cts_i;
output rts_o;
output break_o;
+input flush_i;
reg break_r;
input sio_ce;
input sio_ce_x4;
reg break_r;
input sio_ce;
input sio_ce_x4;
@@
-149,7
+150,7
@@
reg [5:0] rxd_dly; //New input delay used to ensure no baud clocks
//
sasc_fifo4 tx_fifo( .clk( clk ),
//
sasc_fifo4 tx_fifo( .clk( clk ),
- .rst( rst ),
+ .rst( rst && !flush_i ),
.clr( 1'b0 ),
.din( din_i ),
.we( we_i ),
.clr( 1'b0 ),
.din( din_i ),
.we( we_i ),
@@
-160,7
+161,7
@@
sasc_fifo4 tx_fifo( .clk( clk ),
);
sasc_fifo4 rx_fifo( .clk( clk ),
);
sasc_fifo4 rx_fifo( .clk( clk ),
- .rst( rst ),
+ .rst( rst && !flush_i ),
.clr( 1'b0 ),
.din( rxr[9:2] ),
.we( rx_we ),
.clr( 1'b0 ),
.din( rxr[9:2] ),
.we( rx_we ),
@@
-244,7
+245,7
@@
assign break_o = break_r;
always @(posedge clk)
rx_valid <= #1 (rx_bit_cnt == 4'h9) && (rxd_s == STOP_BIT);
always @(posedge clk)
always @(posedge clk)
rx_valid <= #1 (rx_bit_cnt == 4'h9) && (rxd_s == STOP_BIT);
always @(posedge clk)
- break_r <= #1 (rx_bit_cnt == 4'h9) && (rxr[9:1]==8'b0) && (rxd_s == START_BIT);
+ break_r <= #1 (rx_bit_cnt == 4'h9) && (rxr[9:0]==10'b0) && (rxd_dly == 5'b0) && (rxd_s == 0) && (rxd_r == 0);
always @(posedge clk)
rx_valid_r <= #1 rx_valid;
always @(posedge clk)
rx_valid_r <= #1 rx_valid;