some cleanups, build fpga stuff in build/fpga, not src
[fleet.git] / Makefile
index 1c1408c..0bae854 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -25,7 +25,7 @@ fleet.jar: $(shell find src -name \*.java) $(shell find ships -name \*.ship) src
        cd build/class/; jar cmf manifest ../../$@ .
 
 
-## Slipway ####################################################################################
+## Fpga ####################################################################################
 
 #host = sting.eecs.berkeley.edu
 #remote_xilinx = /opt/ISE81/
@@ -39,7 +39,7 @@ remote_dir = /scratch/megacz/fleet/
 #remote_xilinx = /scratch/megacz/xilinx/
 #remote_dir = /scratch/megacz/fleet/
 
-xilinx =  cd build; 
+xilinx =  cd build/fpga;
 xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
 xilinx += XILINX=$(XILINX)
 xilinx += PATH=$$PATH:$(XILINX)/bin/lin
@@ -69,28 +69,29 @@ uploadtest:
 testmegacz:
        $(java) -jar fleet.jar target=fpga bitfile=megacz.bit test ships/*.ship tests
 
-build/fabric.v: $(verilog_files) src/edu/berkeley/fleet/slipway/Slipway.java
+build/fpga/fabric.v: $(verilog_files) src/edu/berkeley/fleet/fpga/Fpga.java
        make fleet.jar
-       mkdir -p build
-       $(java) $(cp) edu.berkeley.fleet.slipway.Slipway > build/fabric.v
+       mkdir -p build/fpga
+       $(java) $(cp) edu.berkeley.fleet.fpga.Fpga > build/fpga/fabric.v
 
-build/main.bit: build/fabric.v $(verilog_files)
+build/main.bit: build/fpga/fabric.v $(verilog_files)
        make fleet.jar
+       cp src/edu/berkeley/fleet/fpga/* build/fpga
        for A in `find ships -name \*.ship`;\
          do java -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\
          done
-       $(java) -cp fleet.jar edu.berkeley.fleet.slipway.Generator
+       $(java) -cp fleet.jar edu.berkeley.fleet.fpga.Generator build/fpga/
        rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
        time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_xilinx}'
        scp ${host}:${remote_dir}/build/main.bit build/
 
 synth:
-       cd build; ln -sf ../src/edu/berkeley/fleet/slipway/* .
-       cd build; echo work > main.lso
-       cd build; for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
-       cd build; mkdir -p tmp
-       cd build; mkdir -p xst
-       rm -rf build/_ngo
+       cd build/fpga; ln -sf ../src/edu/berkeley/fleet/fpga/* .
+       cd build/fpga; echo work > main.lso
+       cd build/fpga; for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
+       cd build/fpga; mkdir -p tmp
+       cd build/fpga; mkdir -p xst
+       rm -rf build/fpga/_ngo
        $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
        $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
        $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
@@ -109,7 +110,7 @@ test:     fleet.jar; $(java) -jar fleet.jar             test ships/*.ship tests
 testfpga: fleet.jar; $(java) -jar fleet.jar target=fpga test ships/*.ship tests
 
 generate: fleet.jar
-       $(java) -cp fleet.jar edu.berkeley.fleet.slipway.Generator
+       $(java) -cp fleet.jar edu.berkeley.fleet.fpga.Generator build/fpga/
 
 ## API docs ####################################################################################