run all tests (including ships directory), add #skip tests where missing

[fleet.git] / Makefile

diff --git a/Makefile b/Makefile
index 29bdbf9..7ee8667 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -31,10 +31,14 @@ fleet.jar: $(shell find src -name \*.java) $(shell find ships -name \*.ship) src
 #remote_xilinx = /opt/ISE81/
 #remote_dir = fleet/
 
-host = mm2.millennium.berkeley.edu
+host = intel2950-5.eecs.berkeley.edu
 remote_xilinx = /scratch/megacz/xilinx/
 remote_dir = /scratch/megacz/fleet/
 
+#host = mm2.millennium.berkeley.edu
+#remote_xilinx = /scratch/megacz/xilinx/
+#remote_dir = /scratch/megacz/fleet/
+
 xilinx =  cd build; 
 xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
 xilinx += XILINX=$(XILINX)
@@ -57,11 +61,13 @@ runfpga: fleet.jar
 
 upload: fleet.jar build/main.bit
        mkdir -p build
-       rsync -zare ssh --progress --verbose build/main.bit root@bee441.cs.berkeley.edu:/var/slipway/megacz.bit
+       rsync -zare ssh --progress --verbose build/main.bit root@bee441.megacz.com:/var/slipway/megacz.bit
 
 uploadtest:
        make upload
-       $(java) -jar fleet.jar target=fpga bitfile=megacz.bit test tests
+       $(java) -jar fleet.jar target=fpga bitfile=megacz.bit test ships/*.ship tests
+testmegacz:
+       $(java) -jar fleet.jar target=fpga bitfile=megacz.bit test ships/*.ship tests
 
 build/fabric.v: $(verilog_files) src/edu/berkeley/fleet/slipway/Slipway.java
        make fleet.jar
@@ -74,7 +80,7 @@ build/main.bit: build/fabric.v $(verilog_files)
          do java -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\
          done
        rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
-       ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_xilinx}'
+       ssh ${host} 'time make -C ${remote_dir} synth XILINX=${remote_xilinx}'
        scp ${host}:${remote_dir}/build/main.bit build/
 
 synth:
@@ -84,19 +90,25 @@ synth:
        cd build; mkdir -p tmp
        cd build; mkdir -p xst
        rm -rf build/_ngo
-       $(xilinx)xst -intstyle ise -ifn main.xst -ofn main.syr < main.xst
-       $(xilinx)ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
-       $(xilinx)map -intstyle ise -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
-       $(xilinx)par -w -intstyle ise -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
-       $(xilinx)bitgen -intstyle ise -d -f main.ut main.ncd
-#      $(xilinx)trce -intstyle ise -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
+       $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
+       $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
+       $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
+       $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
+       $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
+#      $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
+
+
+manual: fleet.jar
+       $(java) -jar fleet.jar doc
+       cd .tmp; TEXINPUTS=$$TEXINPUTS:../doc/ pdflatex *.tex
+       open .tmp/*.pdf
 
 
-doc: fleet.jar
-       $(java) $(cp) edu.berkeley.fleet.doc.Doc < ships/Alu2.ship
+test:     fleet.jar; $(java) -jar fleet.jar             test ships/*.ship tests
+testfpga: fleet.jar; $(java) -jar fleet.jar target=fpga test ships/*.ship tests
 
-test:     fleet.jar; $(java) -jar fleet.jar             test tests/
-testfpga: fleet.jar; $(java) -jar fleet.jar target=fpga test tests/
+generate: fleet.jar
+       $(java) -cp fleet.jar edu.berkeley.fleet.slipway.Generator
 
 ## API docs ####################################################################################