factor out verilog headers on Alu2 ship

[fleet.git] / Makefile

diff --git a/Makefile b/Makefile
index 76dc897..a13ec23 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -53,7 +53,7 @@ runfpga: fleet.jar
 mrunfpga: fleet.jar build/main.bit
        mkdir -p build
        rsync -zare ssh --progress --verbose build/main.bit root@bee441.cs.berkeley.edu:/var/slipway/megacz.bit
-       $(java) -jar fleet.jar bitfile=megacz.bit target=fpga run
+       $(java) -jar fleet.jar bitfile=megacz.bit target=fpga test tests
 
 build/fabric.v: $(verilog_files) src/edu/berkeley/fleet/slipway/Slipway.java
        make fleet.jar