updates for ml410 board

[fleet.git] / Makefile

diff --git a/Makefile b/Makefile
index 276366e..d0f496f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -31,10 +31,14 @@ fleet.jar: $(shell find src -name \*.java) $(shell find ships -name \*.ship) src
 #remote_xilinx = /opt/ISE81/
 #remote_dir = fleet/
 
-host = intel2950-5.eecs.berkeley.edu
+host = intel2950-4.eecs.berkeley.edu
 remote_xilinx = /scratch/megacz/xilinx/
 remote_dir = /scratch/megacz/fleet/
 
+#host = cs61c-tb@ilinux1.eecs.berkeley.edu
+#remote_xilinx = /usr/local/xilinx/xilinx.ise.9.1-1607-8571-0259-2277
+#remote_dir = /home/tmp/cs61c-tb/fleet
+
 #host = mm2.millennium.berkeley.edu
 #remote_xilinx = /scratch/megacz/xilinx/
 #remote_dir = /scratch/megacz/fleet/
@@ -45,6 +49,8 @@ xilinx += XILINX=$(XILINX)
 xilinx += PATH=$$PATH:$(XILINX)/bin/lin
 xilinx += $(XILINX)/bin/lin/
 
+device = xc4vfx60-ff1152
+
 remote_run =  skill a.out;
 remote_run += user_unprogram 1;
 remote_run += user_program 1 main.bit;
@@ -59,15 +65,18 @@ verilog_files += $(shell find src -name \*.inc)
 runfpga: fleet.jar
        $(java) -jar fleet.jar target=fpga run
 
+program: upload
+       ssh root@goliath.megacz.com 'cd /afs/megacz.com/work/ml410/; ./program.sh ./main.bit'
+
 upload: fleet.jar build/fpga/main.bit
        mkdir -p build
-       rsync -zare ssh --progress --verbose build/fpga/main.bit root@bee441.megacz.com:/var/slipway/megacz.bit
+       rsync -zare ssh --progress --verbose build/fpga/main.bit root@goliath.megacz.com:/afs/megacz.com/work/ml410/
 
 uploadtest:
        make upload
-       $(java) -jar fleet.jar target=fpga bitfile=megacz.bit test ships/*.ship tests
+       $(java) -jar fleet.jar target=fpga bitfile=megacz.bit test tests ships/*.ship
 testmegacz:
-       $(java) -jar fleet.jar target=fpga bitfile=megacz.bit test ships/*.ship tests
+       $(java) -jar fleet.jar target=fpga bitfile=megacz.bit test tests ships/*.ship
 
 build/fpga/fabric.v: $(verilog_files) src/edu/berkeley/fleet/fpga/Fpga.java
        make fleet.jar
@@ -86,23 +95,23 @@ build/fpga/main.bit: build/fpga/fabric.v $(verilog_files)
        scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/
 
 synth:
-       cd build/fpga; ln -sf ../src/edu/berkeley/fleet/fpga/* .
+       cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
        cd build/fpga; echo work > main.lso
        cd build/fpga; for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
        cd build/fpga; mkdir -p tmp
        cd build/fpga; mkdir -p xst
        rm -rf build/fpga/_ngo
        $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
-       $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
-       $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
+       $(xilinx)ngdbuild -aul -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
+       $(xilinx)map -intstyle xflow -p $(device) -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
        $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
        $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
 #      $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
 
 
 
-test:     fleet.jar; $(java) -jar fleet.jar             test ships/*.ship tests
-testfpga: fleet.jar; $(java) -jar fleet.jar target=fpga test ships/*.ship tests
+test:     fleet.jar; $(java) -jar fleet.jar             test tests ships/*.ship
+testfpga: fleet.jar; $(java) -jar fleet.jar target=fpga test tests ships/*.ship
 
 generate: fleet.jar
        $(java) -cp fleet.jar edu.berkeley.fleet.fpga.Generator build/fpga/