add XIL_XST_HIDEMESSAGES=hdl_and_low_levels to Makefile

[fleet.git] / Makefile

diff --git a/Makefile b/Makefile
index 440b295..e5b1a9e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -45,6 +45,7 @@ xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(remote_ise)/bin/lin:$(remote_edk)/
 xilinx += PATH=$$PATH:$(remote_ise)/bin/lin:$(remote_edk)/bin/lin
 xilinx += XST_VERSION=9.2i
 xilinx += XILINX=$(remote_ise)
+xilinx += XIL_XST_HIDEMESSAGES=hdl_and_low_levels
 xilinx += XILINX_EDK=$(remote_edk)
 
 xilinx_ise = $(xilinx) $(remote_ise)/bin/lin/
@@ -144,11 +145,33 @@ synth:
        echo -n " -slice_utilization_ratio_maxmargin 5" >> build/fpga/main.xst
        echo >> build/fpga/main.xst
 
+       rm -f build/fpga/main.ut
+       echo '-w' >> build/fpga/main.ut
+       echo '-g CclkPin:PULLUP' >> build/fpga/main.ut
+       echo '-g TdoPin:PULLNONE' >> build/fpga/main.ut
+       echo '-g M1Pin:PULLDOWN' >> build/fpga/main.ut
+       echo '-g DonePin:PULLUP' >> build/fpga/main.ut
+       echo '-g DriveDone:No' >> build/fpga/main.ut
+       echo '-g StartUpClk:JTAGCLK' >> build/fpga/main.ut
+       echo '-g DONE_cycle:4' >> build/fpga/main.ut
+       echo '-g GTS_cycle:5' >> build/fpga/main.ut
+       echo '-g M0Pin:PULLUP' >> build/fpga/main.ut
+       echo '-g M2Pin:PULLUP' >> build/fpga/main.ut
+       echo '-g ProgPin:PULLUP' >> build/fpga/main.ut
+       echo '-g TckPin:PULLUP' >> build/fpga/main.ut
+       echo '-g TdiPin:PULLUP' >> build/fpga/main.ut
+       echo '-g TmsPin:PULLUP' >> build/fpga/main.ut
+       echo '-g DonePipe:No' >> build/fpga/main.ut
+       echo '-g GWE_cycle:6' >> build/fpga/main.ut
+       echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
+       echo '-g Security:NONE' >> build/fpga/main.ut
+       echo '-g Persist:No' >> build/fpga/main.ut
+
        $(xilinx_ise)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
        $(xilinx_ise)ngdbuild -aul -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
        $(xilinx_ise)map -cm area -intstyle xflow -p $(device) -pr b -ol high -o main_map.ncd main.ngd main.pcf
        $(xilinx_ise)par -w -intstyle xflow -t 99 -pl high -rl high main_map.ncd main.ncd main.pcf
-       $(xilinx_ise)bitgen -intstyle xflow -d -f main.ut main.ncd
+       $(xilinx_ise)bitgen -intstyle xflow -f main.ut main.ncd
 #      $(xilinx_ise)trce -intstyle xflow -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
        $(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ml410 -ace mainx.ace
        mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
@@ -282,7 +305,7 @@ runtest: fleet.jar
        rm -f suncvs/marina/testSims/isolatedInDock.spi.run
        ssh simmons 'skill nanosim'
        rsync -are ssh --delete --progress --verbose ./ simmons:~/fleet/
-       ssh simmons 'export PATH=$$PATH:/proj/async/cad/linux/bin/; cd ~/fleet/suncvs/marina/testSims; /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java -cp $$HOME/fleet/fleet.jar:$$HOME/fleet/lib/suncvs.jar com.sun.vlsi.chips.marina.test.MarinaTest -testNum 3001'
+       ssh simmons 'export PATH=$$PATH:/proj/async/cad/linux/bin/; cp -r /import/async/cad/2008/marina/rkao/marina/testSims/* ~/fleet/suncvs/marina/testSims/; cp -r /import/async/cad/2008/marina/rkao/marina/testCode/*.xml ~/fleet/suncvs/marina/testCode/; cd ~/fleet/suncvs/marina/testSims; /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java -cp $$HOME/fleet/fleet.jar:$$HOME/fleet/lib/suncvs.jar com.sun.vlsi.chips.marina.test.MarinaTest -testNum 3004'
 
 suncvs/test:
        mkdir -p suncvs
@@ -291,6 +314,4 @@ suncvs/test:
 suncvs/marina:
        mkdir -p suncvs
        cd suncvs; cvs -d simmons:/import/async/cad/cvs co marina
-       cd suncvs/marina; rsync -are ssh simmons:/import/async/cad/2008/marina/rkao/marina/testSims/ testSims/
-       cd suncvs/marina; rsync -are ssh simmons:/import/async/cad/2008/marina/rkao/marina/testCode/isolatedInDock.xml testCode/