\definecolor{light}{gray}{0.7}
+\setlength{\marginparwidth}{1.2in}
+\let\oldmarginpar\marginpar
+\renewcommand\marginpar[1]{\-\oldmarginpar[\raggedleft\footnotesize #1]%
+{\raggedright\footnotesize #1}}
+
+
\newcommand{\footnoteremember}[2]{
\footnote{#2}
\newcounter{#1}
\begin{tabular}{rl}
\color{red}
-??-Apr
+23-Apr
+& added epilogue fifo to diagrams \\
+& indicated that a token sent to the instruction port is treated as a torpedo \\
+18-Apr
+& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
+& replaced {\tt literal} with {\tt shift} instruction \\
\color{black}
+17-Apr
+& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
+& Removed ability to manually set the {\tt C} flag \\
+& Expanded predicate field to three bits \\
+& New literals scheme (via shifting) \\
+& Instruction encoding changes made at Ivan's request (for layout purposes) \\
+& Added summary of instruction encodings on last page \\
+07-Apr
+& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
+06-Apr
+& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
+& update table 3.1.2 \\
+& rename {\tt S} flag to {\tt C} \\
& noted that {\tt setFlags} can be used as {\tt nop} \\
29-Mar
& removed the {\tt L} flag (epilogues can now do this) \\
& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
& renamed {\tt data} instruction to {\tt literal} \\
& renamed {\tt send} instruction to {\tt move} \\
-23-Mar
-& added ``if its predicate is true'' to repeat count \\
-& added note that red wires do not contact ships \\
-& changed name of {\tt flags} instruction to {\tt setFlags} \\
-& removed black dot from diagrams \\
-& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
-& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
-& indicated that only {\tt send} instructions which wait for data are torpedoable \\
-& added section ``Torpedo Details'' \\
-& removed {\tt torpedo} instruction \\
-12-Mar
-\color{black}
-& renamed loop+repeat to outer+inner (not in red) \\
-& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
-& rewrote ``inner and outer loops'' section \\
-& updated all diagrams \\
-\color{black}
-7-Mar
-& Moved address bits to the LSB-side of a 37-bit instruction \\
-& Added {\it micro-instruction} and {\it composite instruction} terms \\
-& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
-& Created the {\tt Hold} field \\
-& Changed how ReLooping works \\
-& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
+%23-Mar
+%& added ``if its predicate is true'' to repeat count \\
+%& added note that red wires do not contact ships \\
+%& changed name of {\tt flags} instruction to {\tt setFlags} \\
+%& removed black dot from diagrams \\
+%& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
+%& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
+%& indicated that only {\tt send} instructions which wait for data are torpedoable \\
+%& added section ``Torpedo Details'' \\
+%& removed {\tt torpedo} instruction \\
+%12-Mar
+%\color{black}
+%& renamed loop+repeat to outer+inner (not in red) \\
+%& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
+%& rewrote ``inner and outer loops'' section \\
+%& updated all diagrams \\
+%\color{black}
+%7-Mar
+%& Moved address bits to the LSB-side of a 37-bit instruction \\
+%& Added {\it micro-instruction} and {\it composite instruction} terms \\
+%& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
+%& Created the {\tt Hold} field \\
+%& Changed how ReLooping works \\
+%& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
\end{tabular}
\end{abstract}
All instruction words have the following format:
+\newcommand{\bitsHeader}{
+ \bitbox{1}{I}
+ \bitbox{1}{OS}
+ \bitbox{3}{P}
+}
+
\setlength{\bitwidth}{3.5mm}
{\tt \footnotesize
\begin{bytefield}{37}
\bitheader[b]{0,10,11,36}\\
\color{black}
- \bitbox{1}{I}
- \bitbox{1}{OS}
- \bitbox{2}{P}
+ \bitsHeader
\color{light}
- \bitbox[tbr]{22}{}
+ \bitbox[tbr]{21}{}
\bitbox{11}{dispatch path}
\color{black}
\end{bytefield}}
&\side{{\tt setOuter}}
&
\\\hline
-Wait for hatch sealed & + & + & + & + & + & & & & & & \\
-Fill IF0 w/ copy of self & + & + & + & + & + & & & & & & \\\hline
-Request arbiter & P+$\star$ & & & & & P+$\star$ & & & & & \\
-Potentially torpedoable & P+$\star$ & & & & & P+$\star$ & & & & & \\\hline
-Execute & P+ & P+& P+& P+& P+ & ? & ? & ? & ? & P & \\
-Inner-looping & P+ & & & & ? & P+ & & & & ? & \\
+Wait for hatch sealed, & + & + & + & + & + & - & - & - & - & - & \\
+then IF0 w/ copy of self & & & & & & & & & & & \\\hline
+Potentially torpedoable & P+I & P+I & P+I & P+I & P+I & P+I & P+I & P+I & P+I & PI & \\
+Execute & P+ & P+ & P+ & P+ & P+ & P+ & P+ & P+ & P+ & P & \\
+Inner-looping & P+ & - & - & - & - & P & - & - & - & - & \\
\hline
\end{tabular}
+ & Only if {\tt OLC>0} (ie {\tt OLC} is positive) \\
P & Only if predicate is true \\
P+ & Only if predicate is true and {\tt OLC>0} \\
-P+$\star$ & Only if predicate is true and {\tt OLC>0} and {\tt I=1} and one of {\tt Ti},{\tt Di},{\tt Do} true. \\
-? & to discuss \\\hline
+PI & Only if predicate is true and {\tt I=1}. \\
+P+I & Only if predicate is true and {\tt OLC>0} and {\tt I=1}. \\\hline
\end{tabular}
\end{center}
+{\bf Note:} a non-one-shot instruction may {\it execute} before the
+hatch is sealed, but may not {\it fill IF0} before the hatch is
+sealed. The instruction will not vacate On Deck until both of these
+tasks are complete, so the second non-one-shot instruction in a loop
+will not execute until the hatch is sealed, {\it but the first
+ instruction will}.
+\pagebreak
+
+\color{black}
\subsubsection{Torpedo}
-There is a small fifo (not shown) before the latch marked
-``Instruction Horn''; after the {\tt tail} instruction seals the
-hatch, any subsequent instructions will queue up in this fifo until
-the hatch is unsealed. This is typically used as storage for a ``loop
-epilogue'' -- a sequence of instructions to be executed after a
-torpedo arrives or the outer loop counter expires.
+There is a small fifo marked ``Epilogue'' just beyond the instruction
+destination; after the {\tt tail} instruction seals the hatch, any
+subsequent instructions will queue up in this fifo until the hatch is
+unsealed. This is typically used as storage for a ``loop epilogue''
+-- a sequence of instructions to be executed after a torpedo arrives
+or the outer loop counter expires.
+
+A {\it token} sent to a ship's instruction destination is treated as a
+torpedo; the check for a torpedo is performed {\it before} the head of
+the Epilogue fifo. Note that because the check for a token is
+performed ``upstream'' of the epilogue fifo, torpedos will still be
+effective even when the Epilogue fifo is nearly full.
+\color{black}
-Each dock has a fourth connection to the switch fabric (not shown),
-called its {\it torpedo destination}. Anything (even a token) sent to
-this destination is treated as a torpedo. Note that because this is a
-distinct destination, instructions or data queued up in the other
-destination fifos will not prevent a torpedo from occuring.
+The dock also has a {\it torpedo acknowledgment path latch},
+which stores the path along which a token should be sent when a
+torpedo strikes.
When a data item or token arrives at the torpedo destination, it lies
there in wait until On Deck holds a potentially torpedoable
instruction (see previous table). Once this is the case, the torpedo
causes the inner and outer loop counters to be set to zero (and
-therefore also unseals the hatch).\footnote{it is unspecified whether
+therefore also unseals the hatch)\footnote{it is unspecified whether
the torpedoed instruction is requeued or not; this may or may not
occur, nondeterministically. It is the programmer's responsibility
to ensure that the program behaves the same whether this happens or
- not. We think that this will not matter in most situations.}
+ not. We think that this will not matter in most situations.} and
+sends a token along the path stored in the torpedo acknowledgment path
+latch.
-\color{black}
\subsection{Flags}
-The pump has three flags: {\tt A}, {\tt B}, and {\tt S}.
+The pump has three flags: {\tt A}, {\tt B}, and {\tt C}.
\begin{itemize}
\item The {\tt A} and {\tt B} flags are general-purpose flags which
% operations (such as sending a completion token) only on the last
% iteration of an outer loop.
-\item The {\tt S} flag, known as the {\it summary} flag. Its value is
- determined by the ship, but unless stated otherwise, it should
- be assumed that whenever the 37th bit of the data ({\tt D})
- latch is loaded, that same bit is also loaded into the {\tt S}
- flag. This lets the ship make decisions based on whether or not
- the top bit of the data latch is set; if two's complement
- numbers are in use, this will indicate whether or not the
- latched value is negative.
+\item The {\tt C} flag is known as the {\it control} flag, and it is
+ set every time the data latch takes on a new value. At outboxes
+ its value is determined by the ship; at inboxes its value is
+ copied from an unused address bit in the destination to which
+ the received value was sent.
\end{itemize}
-Many instruction fields are specified as two-bit {\it predicates}.
-These fields contain one of four values, indicating if an action
-should be taken unconditionally or conditionally on one of the {\tt A}
-or {\tt B} flags:
+Many instruction fields are specified as
+three-bit {\it predicates}. These fields
+contain one of eight values, indicating if an action should be taken
+unconditionally or conditionally on one of the {\tt A}, {\tt B}, or
+{\tt C} flags:
+\begin{multicols}{2}
\begin{itemize}
-\item {\tt 00:} if {\tt A} is set
-\item {\tt 10:} if {\tt B} is set
-\item {\tt 01:} TBD
-\item {\tt 11:} always
+\item {\tt 000:} if {\tt A} is set
+\item {\tt 001:} if {\tt A} is cleared
+\item {\tt 010:} if {\tt B} is set
+\item {\tt 011:} if {\tt B} is cleared
\end{itemize}
+\begin{itemize}
+\item {\tt 100:} if {\tt C} is set
+\item {\tt 101:} if {\tt C} is cleared
+\item {\tt 110:} unused
+\item {\tt 111:} always
+\end{itemize}
+\end{multicols}
+\color{black}
\pagebreak
\begin{center}
\begin{tabular}{|l|}\hline
{\tt move} (variants: {\tt moveto}, {\tt dispatch}) \\
-{\tt literal} (variants: {\tt literalhi}, {\tt literallo})\\
+{\tt literal}\\
{\tt setFlags} \\
{\tt setInner} \\
{\tt setOuter} \\
\end{tabular}
\end{center}
-{\tt tail} {\it will probably become a bit on every instruction rather than
- its own instruction}
-
\color{black}
\subsection{{\tt move} (variants: {\tt moveto}, {\tt dispatch})}
-\setlength{\bitwidth}{5mm}
+\newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
- \bitheader[b]{12-16,19,21}\\
+ \bitheader[b]{14-20}\\
\color{light}
- \bitbox{1}{I}
- \bitbox{1}{OS}
- \bitbox{2}{P}
-\color{black}
- \bitbox{3}{001}
-\color{light}
- \bitbox[trb]{2}{}
+ \bitsHeader
\color{black}
+ \bitbox{1}{0}
+ \bitbox{1}{1}
\bitbox{1}{\tt Ti}
\bitbox{1}{\tt Di}
\bitbox{1}{\tt Dc}
\bitbox{1}{\tt Do}
\bitbox{1}{\tt To}
- \bitbox[l]{17}{}
+ \bitbox[l]{19}{}
\end{bytefield}}
-%\begin{bytefield}{26}
-% \bitheader[b]{12-18}\\
-% \bitbox[]{8}{\raggedleft Input Dock:}
-% \bitbox[r]{2}{}
-% \bitbox{1}{\tt So}
-% \bitbox{1}{\tt Dc}
-% \bitbox[l]{15}{}
-%\end{bytefield}
-%
-%\begin{bytefield}{26}
-% \bitheader[b]{12-18}\\
-% \bitbox[]{8}{\raggedleft Output Dock:}
-% \bitbox[r]{2}{}
-% \bitbox{1}{\tt Si}
-% \bitbox{1}{\tt To}
-% \bitbox[l]{15}{}
-%\end{bytefield}
-
\begin{bytefield}{26}
- \bitheader[b]{0,10,11}\\
- \bitbox[1]{13}{\raggedleft {\tt moveto} ({\tt LiteralPath\to Path})}
+ \bitheader[b]{0,12,13}\\
+ \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt LiteralPath\to Path})}
\bitbox[r]{1}{}
\bitbox{1}{\tt 1}
- \bitbox{11}{\tt LiteralPath}
+ \bitbox{13}{\tt LiteralPath}
\end{bytefield}
\begin{bytefield}{26}
- \bitheader[b]{10,11}\\
- \bitbox[1]{13}{\raggedleft {\tt dispatch} ({\tt DP[37:27]\to Path})\ \ }
+ \bitheader[b]{11,12,13}\\
+ \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\tt DP[37:25]\to Path})\ \ }
\bitbox[r]{1}{}
\bitbox{1}{\tt 0}
\bitbox{1}{\tt 1}
+ \bitbox{1}{\tt 0}
\color{light}
- \bitbox[trb]{10}{}
+ \bitbox[trb]{11}{}
\color{black}
\end{bytefield}
\begin{bytefield}{26}
- \bitheader[b]{10,11}\\
- \bitbox[1]{13}{\raggedleft {\tt move} ({\tt Path} unchanged):}
+ \bitheader[b]{11,12,13}\\
+ \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
\bitbox[r]{1}{}
\bitbox{1}{\tt 0}
\bitbox{1}{\tt 0}
+ \bitbox{1}{\tt 1}
\color{light}
- \bitbox[trb]{10}{}
+ \bitbox[trb]{11}{}
\color{black}
-\end{bytefield}
+\end{bytefield}}
+\bitsMove
\begin{itemize}
\item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
\pagebreak
-\subsection{{\tt literal}, {\tt literalhi}, {\tt literallo}}
-These instructions load part or all of the data latch ({\tt D}).
+\subsection{{\tt set}}
-{\tt literalhi: Literal[18:1]\to D[37:20]} (and {\tt Literal[18]\to S})
+The {\tt set} command is used to set or decrement the inner loop
+counter, outer loop counter, and data latch.
+\newcommand{\bitsSet}{
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
- \bitheader[b]{0,18,19,21}\\
+ \bitheader[b]{0,14-15,16-20}\\
\color{light}
- \bitbox{1}{I}
- \bitbox{1}{OS}
- \bitbox{2}{P}
+ \bitsHeader
\color{black}
+ \bitbox{1}{1}
\bitbox{1}{0}
- \bitbox{2}{11}
-\color{light}
- \bitbox[trb]{1}{}
+ \bitbox{2}{SRC}
+ \bitbox{2}{DST}
\color{black}
- \bitbox{18}{Literal}
+ \bitbox{15}{Payload}
\end{bytefield}}
+}
+\bitsSet
-{\tt literallo: Literal[19:1]\to D[19:1]}
+\begin{center}{\tt
+\begin{tabular}{|r|r|l|l|}\hline
+Source & SRC & DST & Destination \\\hline
+\hline
+Payload & 00 & 00 & OLC \\
+Data Latch & 01 & 00 & OLC \\
+OLC-1 & 10 & 00 & OLC \\
+Payload & 00 & 01 & ILC \\
+Data Latch & 01 & 01 & ILC \\
+$\infty$ & 10 & 01 & ILC \\
+Payload & 00 & 10 & Torpedo Ack Path \\
+Payload, 0-extend & 01 & 10 & Data Latch \\
+Payload, 1-extend & 10 & 10 & Data Latch \\
+ see below & & 11 & Flags \\
+\hline
+\end{tabular}
+}\end{center}
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{0,18,19,21}\\
-\color{light}
- \bitbox{1}{I}
- \bitbox{1}{OS}
- \bitbox{2}{P}
-\color{black}
- \bitbox{1}{0}
- \bitbox{2}{10}
- \bitbox{19}{Literal}
-\end{bytefield}}
+The FleetTwo implementation is likely to have an unarchitected
+``literal latch'' at the OD stage, which is loaded with the
+possibly-extended literal {\it at the time that the {\tt set}
+ instruction comes on deck}. This latch is then copied into the data
+latch when the instruction executes.
-{\tt literal:}
+If the {\tt Dest} field is flags, the {\tt Payload} field is
+interpreted as two fields, each giving the truth table for the new
+value of one of the two user-settable flags:
+\begin{center}
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
- \bitheader[b]{0,18,19,21}\\
+ \bitheader[b]{0,5,6,11}\\
\color{light}
- \bitbox{1}{I}
- \bitbox{1}{OS}
- \bitbox{2}{P}
+ \bitsHeader
+ \bitbox{1}{1}
+ \bitbox{1}{0}
+\color{light}
+ \bitbox{2}{}
\color{black}
- \bitbox{1}{1}
- \bitbox{2}{SEL}
- \bitbox{19}{Literal}
-\end{bytefield}}
-
-{\tt
-\begin{tabular}{|r|c|c|c|}\hline
-sel & D[37:20] & D[19:1] \\\hline
-00 & Literal[18:1] & all 0 \\
-01 & Literal[18:1] & all 1 \\
-10 & all 0 & Literal[19:1] \\
-11 & all 1 & Literal[19:1] \\
-\hline
-\end{tabular}}
-
-
-
-
-\subsection{{\tt setFlags}}
-
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{0,7,8,15,16-19,21}\\
+ \bitbox{2}{11}
\color{light}
- \bitbox{1}{I}
- \bitbox{1}{OS}
- \bitbox{2}{P}
+ \bitbox{3}{}
\color{black}
- \bitbox{3}{000}
- \bitbox{1}{0}
\bitbox{6}{nextA}
\bitbox{6}{nextB}
- \bitbox{6}{nextS}
\end{bytefield}}
-
-The {\tt P} field is a predicate; if it does not hold, the instruction
-is ignored. Otherwise the flags are updated according to the {\tt
- nextA}, {\tt nextB}, and {\tt nextS} fields; each specifies the new
-value as the logical {\tt OR} of zero or more inputs:
+\end{center}
+\color{black}
+Each field has the following structure, and indicates which old flag
+values should be logically {\tt OR}ed together to produce the new flag
+value:
\begin{center}
{\tt
\bitbox{1}{$\overline{\text{\tt A}}$}
\bitbox{1}{${\text{\tt B}}$}
\bitbox{1}{$\overline{\text{\tt B}}$}
- \bitbox{1}{${\text{\tt S}}$}
- \bitbox{1}{$\overline{\text{\tt S}}$}
+ \bitbox{1}{${\text{{\tt C}\ }}$}
+ \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
\end{bytefield}}
\end{center}
set are {\tt OR}ed together, and the resulting value is assigned to
the flag. Note that if none of the bits are set, the value assigned
is zero. Note also that it is possible to produce a {\tt 1} by {\tt
- OR}ing any flag with its complement.
-\color{red}
-Note that {\tt setFlags} can be used to create a {\tt nop} (no-op) by
-setting each flag to itself.
-\color{black}
-
+ OR}ing any flag with its complement, and that {\tt set Flags} can
+be used to create a {\tt nop} (no-op) by setting each flag to itself.
-\pagebreak
-
-\subsection{{\tt setInner}}
-
-This instruction loads the inner loop counter with either a literal
-number, the special value $\infty$, or the contents of the {\tt data}
-register.
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{16-19,21}\\
-\color{light}
- \bitbox{1}{I}
- \bitbox{1}{OS}
- \bitbox{2}{P}
-\color{black}
- \bitbox{3}{000}
- \bitbox{1}{1}
- \bitbox{2}{01}
-\color{light}
- \bitbox[tbr]{8}{}
- \bitbox[l]{8}{}
\color{black}
-\end{bytefield}}\\
-
-\begin{bytefield}{26}
- \bitbox[r]{18}{\raggedleft from data latch:\hspace{0.2cm}\ }
- \bitbox{2}{\tt 00}
-\color{light}
- \bitbox[tbr]{6}{}
-\color{black}
-\end{bytefield}
-
-\begin{bytefield}{26}
- \bitheader[b]{0,5,6,7}\\
- \bitbox[r]{18}{\raggedleft from literal:\hspace{0.2cm}\ }
- \bitbox{2}{\tt 10}
- \bitbox{6}{\tt Literal}
-\end{bytefield}
-
-\begin{bytefield}{26}
- \bitheader[b]{0,5,6,7}\\
- \bitbox[r]{18}{\raggedleft with $\infty$\ \ }
- \bitbox{2}{\tt 11}
-\color{light}
- \bitbox[tbr]{6}{}
-\color{black}
-\end{bytefield}
+\pagebreak
+\subsection{{\tt shift}}
-\subsection{{\tt setOuter}}
+\newcommand{\shiftPayloadSize}{19}
-This instruction loads the outer loop counter {\tt OLC} with either
-{\tt max(0,OLC-1)}, a literal or the contents of the {\tt data}
-register.
+Each {\tt shift} instruction carries a payload of \shiftPayloadSize\
+bits. When a {\tt shift} instruction is executed, this payload is copied
+into the least significant \shiftPayloadSize\ bits of the data latch,
+and the remaining most significant bits of the data latch are loaded
+with the value formerly in the least significant bits of the data latch.
+In this manner, large literals can be built up by ``shifting'' them
+into the data latch \shiftPayloadSize\ bits at a time.
+\newcommand{\bitsShift}{
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
- \bitheader[b]{16-19,21,24}\\
+ \bitheader[b]{0,18-20}\\
\color{light}
- \bitbox{1}{I}
- \bitbox{1}{OS}
-\color{light}
- \bitbox[tbr]{2}{P}
+ \bitsHeader
\color{black}
- \bitbox{3}{000}
- \bitbox{1}{1}
- \bitbox{2}{10}
-\color{light}
- \bitbox[tbr]{9}{}
- \bitbox[l]{7}{}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
\color{black}
-\end{bytefield}}\\
+ \bitbox{\shiftPayloadSize}{Payload}
+\end{bytefield}}
+}
+\bitsShift
-\begin{bytefield}{26}
- \bitbox[r]{19}{\raggedleft {\tt max(0,OLC-1)}:\hspace{0.2cm}\ }
- \bitbox{2}{\tt 00}
-%\color{light}
- \bitbox[tbr]{5}{}
-%\color{black}
-\color{black}
-\end{bytefield}
+The FleetTwo implementation is likely to have an unarchitected
+``literal latch'' at the OD stage, which is loaded with the literal
+{\it at the time that the {\tt shift} instruction comes on deck}.
+This latch is then copied into the data latch when the instruction
+executes.
-\begin{bytefield}{26}
- \bitbox[r]{19}{\raggedleft from data latch:\hspace{0.2cm}\ }
- \bitbox{2}{\tt 01}
-\color{light}
- \bitbox[tbr]{5}{}
\color{black}
-\end{bytefield}
-
-\begin{bytefield}{26}
- \bitheader[b]{0,5,6}\\
- \bitbox[r]{19}{\raggedleft from literal:\hspace{0.2cm}\ }
- \bitbox{1}{\tt 1}
- \bitbox{6}{\tt Literal}
-\end{bytefield}
-
-
-%\subsection{{\tt torpedo}}
-%
-%\setlength{\bitwidth}{5mm}
-%{\tt
-%\begin{bytefield}{26}
-% \bitheader[b]{0,5,16-19,21}\\
-%\color{light}
-% \bitbox{4}{}
-%\color{black}
-% \bitbox{3}{000}
-% \bitbox{1}{1}
-% \bitbox{2}{00}
-%\color{light}
-% \bitbox[tbr]{16}{}
-%\end{bytefield}}
-%
-%
-%When a {\tt torpedo} instruction reaches the instruction horn, it will
-%wait there until an instruction is on deck whose {\tt A}rmor bit is
-%not set. The {\tt torpedo} will then cause ``Process \#2'' of the on
-%deck instruction to terminate and will set the outer loop counter to zero.
\subsection{{\tt tail}}
-{\it This will probably become a bit on every instruction rather than
- its own instruction. The only problem is that we have run out of bits in the {\tt literal} instruction. Two possible solutions: (a) declare that {\tt literal} cannot be the last instruction in a loop or (b) because {\tt literal} instructions cannot be torpedoed anyways, re-use its {\tt I} bit for this purpose.}
-
+\newcommand{\bitsTail}{
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
- \bitheader[b]{0,5,16-19,21}\\
+ \bitheader[b]{19-20}\\
\color{light}
- \bitbox{4}{}
+ \bitbox{5}{}
\color{black}
- \bitbox{3}{000}
\bitbox{1}{1}
- \bitbox{2}{01}
+ \bitbox{1}{1}
\color{light}
- \bitbox[tbr]{16}{}
-\end{bytefield}}
+ \bitbox[tbr]{19}{}
+\end{bytefield}}}
+\bitsTail
When a {\tt tail} instruction reaches {\tt IH}, it seals the hatch.
The {\tt tail} instruction does not enter the instruction fifo.
\pagebreak
+\section*{Instruction Encoding Map\color{black}}
+
+\hspace{-1cm}{\tt move}\\
+\bitsMove
+
+\hspace{-1cm}{\tt shift}\\
+\bitsShift
+
+\hspace{-1cm}{\tt set}\\
+\bitsSet
+
+\hspace{-1cm}{\tt tail}\\
+\bitsTail
+
+
+\color{black}
+
+\pagebreak
\epsfig{file=overview,height=5in,angle=90}
\pagebreak
projects / fleet.git / blobdiff