--- /dev/null
+// megacz@cs.berkeley.edu, public domain
+
+module root(clk,
+ read_empty, read_enable, read_data,
+ write_full, write_enable, write_data);
+
+ input clk;
+ input read_empty;
+ input write_full;
+ output read_enable;
+ output write_enable;
+ input [7:0] read_data;
+ output [7:0] write_data;
+
+ reg read_enable_;
+ assign read_enable = read_enable_;
+ reg write_enable_;
+ assign write_enable = write_enable_;
+ reg [7:0] write_data_;
+ assign write_data = write_data_;
+
+ initial read_enable_ = 1;
+ initial write_enable_ = 0;
+
+ always @(posedge clk) begin
+
+ // if there's stuff to read and room to write, read a byte,
+ // increment it, and write it
+ if (!read_enable_ && !write_enable_ && !read_empty && !write_full) begin
+ read_enable_ <= 1;
+ write_enable_ <= 1;
+ write_data_ <= read_data + 1;
+
+ // else do nothing
+ end else begin
+ read_enable_ <= 0;
+ write_enable_ <= 0;
+
+ end
+
+ end
+
+endmodule